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2.4-GHz and 5.2-GHz Monolithic CMOS Front-End RFICs for Wireless LAN
本論文研究的重點是射頻接收機前端電路之設計。內容分三部份，首先是射頻接收機基本架構及效能參數介紹，對各架構做一番剖析，並且說明接收機效能參數之定義。接著，利用雙降頻式接收機架構設計工作在2.4-GHz頻帶射頻前端電路單晶片，前端電路包括低雜訊放大器及混頻器，並分別闡述各電路原理及其設計方法，再經由量測測試晶片電路之可行性。最後，實現雙頻帶共存低雜訊放器及雙頻帶接收機前端電路。其中2.4-GHz/5.2-GHz雙頻帶共存低雜訊放大器經測試，得到增益分別為8 dB及0 dB，雜訊指數為4.7 dB及5.6 dB。另外，雙頻帶前端電路包含雙頻帶低雜訊放大器及混頻器，其中雙頻帶低雜訊放放大器包含兩個輸入埠，並且可由控制電壓來調整開關式共振器改變其工作頻率。開關式共振器通常被使用來調整低雜訊放大器，使其可產生低增益模式及高增益模式。
The WLAN is riper in the wireless transmission technology at present. In general, the operating frequency range includes 2.4-GHz and 5-GHz frequency band, respectively. In order to move towards the single chip of radio frequency for dual-band or multi-band applications, the demand is more and more upgrading systematically in future. Multi-standard RF receivers are predicted to play a critical role in wireless communication.
The research of the dissertation is focused on the design of the monolithic RF front-end receiver. The content is divided into three parts. Firstly, the basic structures of the RF receiver and efficiency parameter are introduced and analysized, then are state the definition of the efficiency parameters of the receiver. Secondly, based on the dual-conversion structure, the single chip of a 2.4-GHz RF front-end containing LNA and mixer is implemented in 0.18 CMOS technology. The design of the front-end circuit is described in detail, and experiments prove the function of the chip. Finally, we realize a dual-band concurrent LNA and dual-band front-end receiver. For the 2.4-GHz/5.2-GHz dual-band concurrent LNA, the measured gains are 8 dB and 0 dB, the measured noise are 4.7 dB and 5.6 dB. The front-end contains a dual-band LNA and a mixer. The dual-band LNA with two inputs is tuned to the two resonant frequencies by controlling the voltage on a switched resonator. The same switched resonator is also used to switch the LNA between high-gain and low-gain modes.
|Appears in Collections:||電機工程學系所|
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