Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7592
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dc.contributor鄭立德zh_TW
dc.contributor王忠炫zh_TW
dc.contributor.advisor翁芳標zh_TW
dc.contributor.author張力仁zh_TW
dc.contributor.authorChang, Li-Jenen_US
dc.contributor.other中興大學zh_TW
dc.date2008zh_TW
dc.date.accessioned2014-06-06T06:40:14Z-
dc.date.available2014-06-06T06:40:14Z-
dc.identifierU0005-2108200717205200zh_TW
dc.identifier.citation[1] ETSI, EN 300 744 V1.5.1, “Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television” [2] Uwe Ladebusch and Claudia A. Liss, “Terrestrial DVB (DVB-T): a broadcast technology for stationary portable and mobile use,” Proceedings of the IEEE, vol. 94, Issue 1, pp. 183 - 193, Jan. 2006 [3] Ulrich Reimers, Digital Video Broadcasting (DVB); The International Standard for Digital Television, Springer, 2001 [4] Shousheng He and Mats Torkelson, “A New Approach to Pipeline FFT Processor,”10th International Parallel Processing Symposium (IPPS '96), pp. 766 - 770, April 1996 [5] Shousheng He and Mats Torkelson, “Design and Implementation of a 1024-point Pipeline FFT Processor," IEEE Custom Integrated Circuits Conference, pp. 7.5.1 - 7.5.4, May 1998 [6] Horvath, L., Dhaou, I.B., Tenhunen, H. and Isoaho, J., “A Novel, High-speed, Reconfigurable Demapper-Symbol Deinterleaver Architecture for DVB-T,” Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 4, pp. 382 - 385, June 1999 [7] Dalia A. El-Dib and M. I. Elmasry, “Memoryless Viterbi Decoder,” IEEE Transactions on Circuits and Systems, vol. 52, No. 12, Dec. 2005 [8] Jae-Sun Han, Tae-Jin Kim and Chanho Lee, “High Performance Viterbi Decoder using Modified Register Exchange Methods,” ISCAS'04 on Circuits. and Systems, vol.3, pp. 23 - 26, May 2004 [9] Chanho Lee, “A Viterbi Decoder with Efficient Memory Management,” ETRI Journal, vol. 26, No. 1, pp. 21 - 26, Feb. 2004 [10] M. Kivioja, J. Isoaho and L. Vanska, “Design and Implementation of Viterbi Decoder with FPGAs,” Journal of VLSI Signal Processing, vol. 21, No. 1, pp. 5 - 14, May 1999 [11] Gerard K. Rauwerda and Gerard J.M. Smit., “Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware,” Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'05), pp. 62 - 68, Jun 2005 [12] T. K. Truong, Ming-Tang Shih, Irving S. Reed and E. H. Satorius, “A VLSI Design for a Trace-Back Viterbi Decoder,” IEEE Transactions on Communications, vol. 4, No. 3, pp. 616 - 624, Mar. 1992 [13] R. Simon Sherratt, “Performance and Conformance Results of the Deterministic DVB-T Equalizer,” IEEE Transactions on Consumer Electronics, vol. 50, No. 1, pp. 95 - 99, Feb. 2004 [14] J.B. Kim, Y.J. Lim and M.H. Lee, “A Low Complexity FEC Design for DAB,” Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 4, Sydney, Australia, pp. 522 - 525, May 2001 [15] I.S. Reed, M.T. Shih and T.K. Truong, “VLSI design of inverse-free Berlekamp-Massey algorithm,” IEE Proceedings-E, vol. 138, No. 5, Sep. 1991 [16] Dilip V. Sarwate and Naresh R. Shanbhag, “High-Speed Architectures for Reed-Solomon Decoders,” IEEE Transactions on VLSI Systems, vol. 9, No. 5, Oct. 2001zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/7592-
dc.description.abstract數位電視地面廣播系統與一般的數位通訊傳輸系統相似,大至可分成兩大部份,為通道編碼/解碼及調變/解調變。本論文提出了數位電視地面廣播系統(DVB-T)基頻接收器的實現,包括快速傅立葉轉換(FFT)、解交織器、前向糾錯(FEC)、解擾碼器等電路。我們利用Matlab建構出一個軟體系統層級的模擬環境,並且藉此評估整體效能,接著利用Verilog實現整體系統。整個設計流程包括硬體描述語言程式設計、功能模擬、佈局與繞線、時序模擬和燒錄到板子上全倚賴Xilinx ISE和ModelSim這兩套開發工具。而最後電路是利用Xilinx HW-AFX-FF1148-400開發板上的Virtex-4 FPGA晶片來實現。zh_TW
dc.description.abstractThe DVB-T system is similar to most of the prior digital communication systems. It is roughly divided into two major parts, one for channel coding/decoding, and the other for modulation/demodulation. In this thesis, an implementation of a baseband receiver for DVB-T systems is presented. The receiver includes FFT, deinterleavers, FECs, and descrambler. We utilize Matlab to establish a software system-level simulation environment and use this system simulation model to evaluate performance. Furthermore, we implement total system with Verilog HDL. The design process such as Verilog HDL programming, functional simulation, place and route, timing simulation and device programming are completed with Xilinx ISE 7.1i and ModelSim SE 6.0d. The circuit was implemented with the Xilinx Virtex-4 XC4VLX100-10FF1148C Field-Programmable Gate Array (FPGA) device on Xilinx HW-AFX-FF1148-400 proto board.en_US
dc.description.tableofcontents摘要i Abstract ii CONTENTS iii LIST OF TABLES v LIST OF FIGURES vi 1 INTRODUCTION 1 2 DVB-T STANDARD 3 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Outer Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Outer Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Inner Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Inner Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6.1 Bit-wise Interleaving . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6.2 Symbol Interleaver . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 Mapping and Hierarchical Modulation . . . . . . . . . . . . . . . . . . . 18 2.8 OFDM Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 Hardware Design and Implementation 23 3.1 FPGA Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Fast Fourier Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Demapper and Inner Deinterleaver . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 Demapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 Symbol Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.3 Bit Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5 Outer Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Simulation and Verification 39 4.1 System Simulation using Matlab . . . . . . . . . . . . . . . . . . . . . . 39 4.2 FPGA Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 Conclusions and Future Work 45 REFERENCES 46zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2108200717205200en_US
dc.subjectFPGAen_US
dc.subjectFPGAzh_TW
dc.subjectDVB-Ten_US
dc.subjectXilinx ISEen_US
dc.subjectVerilogen_US
dc.subjectFFTen_US
dc.subjectFECen_US
dc.subject數位電視地面廣播系統zh_TW
dc.subjectXilinx ISEzh_TW
dc.subjectVerilogzh_TW
dc.subject快速傅立葉轉換zh_TW
dc.subject前向糾錯zh_TW
dc.title數位電視地面廣播系統基頻接收機之設計與FPGA實現zh_TW
dc.titleDesign and FPGA Implementation of DVB-T Baseband Receiveren_US
dc.typeThesis and Dissertationzh_TW
item.grantfulltextnone-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.languageiso639-1en_US-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
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