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標題: 光纖接收器前端元件之設計與實現
Design and Implementation of Frond-end Components for Optical Receivers
作者: 吳信明
Wu, Hsin-Ming
關鍵字: 光纖接收器前端元件;Optical Receivers
出版社: 電機工程學系所
引用: Bibliography [1]Y. Liu, H. Yang, High-speed optical transceivers, World Scientific, 2006. [2]Eduard Sackinger, Broadband Circuit for Optical Fiber Communication, WILEY INTERSCIENCE, 2005. [3]M. Neuhauser, H.-M. Rein, H. Wrenz. Low-Noise, High-Gain Si Bipolar Preamplifier for 10 Gb/s Optical Fiber Links - Design and Realization, IEEE Journal of Solid-State Circuits, vol. 31, pp. 24-29, January 1996. [4]Helen Kim and Jonathan Bauman. A 12 GHz, 30dB modular BiCMOS limiting amplifier for 10Gb/s SONET receiver. In ISSCC Dig. Tech. Papers, pages 160-161, February 2000. [5]T.H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998. [6]R. Jindal. Gigahertz-Band High-Gain Low-Noise AGC Amplifier in Fine Line NMOS, IEEE Journal of Solid-State Circuits, vol. 22, pp. 512-521, Aug. 1987. [7]C.-K. Wang, P.-C. Huang and C.-Y. Huang. A BICMOS Limiting Amplifier for SONET OC-3, IEEE Journal of Solid-State Circuits, vol. 31, pp. 1076-1090, Aug. 1996. [8]R. Reimann and H. Rein. Bipolar High Gain Limiting Amplifier IC for Optical-Fiber Receiver Operating up to 4Gb/s, IEEE Journal of Solid-State Circuits, vol. 22, pp. 504-511, Aug. 1987. [9]M. Nakamura, N. Ishihara, Y. Akazawa and H. Kimura. An Instantaneous Response CMOS Optical Receiver IC with Wide Dynamic Range and Extremely High Sensitivity Using Feed-Forward Auto-Bias Adjustment, IEEE Journal of Solid-State Circuits, vol. 30, pp. 991-997, Aug. 1995. [10]Y.-H. Chen. Analog Front End Circuit for Pager System Application, Master Thesis, National Central University, 1998. [11]S.-J. Song, S.-M. Park, and H.-J. Yoo. A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique, IEEE Journal Solid-State Circuits, vol. 38, pp. 1213-1219, July 2003. [12]S. H. Lee, M. S. Hwang, Y. Choi, S. Kim, Y. Moon, B. J. Lee, D. K. Jeong, W. Kim, Y. J. Park, and G. Ahn. A 5 Gb/s 0.25 _m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit, IEEE Journal Solid-State Circuits, vol. 37, pp. 1822-1830, Dec. 2002. [13]J. E. Rogers and J. R. Long. A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18-um CMOS, IEEE Journal Solid-State Circuits, vol. 37, pp. 1781-1789, May 2002. [14]J. Savoj and B. Razavi. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector, IEEE Journal Solid-State Circuits, vol. 36, pp. 761-767, May 2001. [15]C. R. Hogge. A self correcting clock recovery circuit, IEEE J. Lightwave Technology, vol. 3, pp. 1312-1314, Dec. 1985. [16]B. Razavi. Challenges in the design of high-speed clock and data recovery circuits, IEEE Comm. Mag., Aug. 2002. [17]M.S. Yuan. CMOS timing recovery for SONET OC-3, M.S. Thesis, National Taiwan University, 2000. [18]Http:// [19]Http:// [20]Http:// [21]F. Herzel, B. Razavi. A Study of Oscillator Jitter Due to Supply and Substrate Noise, IEEE Trans. Circuits and Systems, Part II, vol. 46, pp. 56-62, Jan. 1999. [22]J.-W. Chen. A Tracking Data Recovery System for Inter-Chip Singaling, MS, Thesis, National Taiwan University, June 2000. [23]Http:// [24]Http:// [25]S. Galal and B. Razavi. 10-Gb/s limiting amplifier and laser/modulator driver in 0.18umCMOS technology, in ISSCC Dig. Tech. Papers,pp. 188 - 189, Feb. 2003. [26]W.-Z. Chen, Y.-L. Cheng, and D.-S. Lin. A 1.8-V 10-Gb/s fully integrated CMOS optical Receiver analog front-end, IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1383-1396, Nov. 2005. [27]E. A. Crain. Fast Offset Compensation for 10 Gbps Limit Amplifier ,MIT master thesis, May 2004. [28]C. D. Holdenried,J. W. Haslett,M. W. Lynch. Analysis and design of HBT Cherry-Hooper amplifier with emitter-follower feedbsck for optical communications, IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1959-1967, Nov. 2004. [29]Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, and Thomas H. Lee. Bandwidth Extension in CMOS with Optimized On-Chip Inductors, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 346-355, Mar. 2004. [30]T. Savoj, B. Razavi, High-speed CMOS circuits for Optical Receivers” Kluwer Academic Publishers, 2001. [31]D.-Y Jeong, S.-H. Chai, W.-C Song and G.-H Cho. CMOS Current-Controlled Oscillators Using Multiple-Feedback Loop Architectures, IEEE Int. Solid-State Circuit Conference Dig. Tech. Papers, 1997, pp. 386-387. [32]B. Razavi. A Study of Phase Noise in CMOS Oscillator, IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, Mar. 1996. [33]B. W. Garlepp et al.. A Protable Digital DLL for High-Speed CMOS Interface Circuits, IEEE J. Solid-State Circuits, vol. 34, no. 5, Jan. 1999. [34]B. Razavi. , RF Microelectronics, pp.295, 1998, Prentice Hall PTR.
首先在本篇論文設計一個3.125GHz應用於光纖接收的限制放大器。本限制放大器使用TSMC 0.18-μm CMOS製程進行模擬,並設計3dB頻寬為3.125GHz和增益為45dB,總功率消耗為95mW與1.8V的供應電壓。
其次,設計一個10Gb/s應用於光纖接收端的接收器,包括轉阻放大器(TIA)和限制放大器(LA)組成並且使用TSMC SiGe0.35-µm 製程進行模擬, 轉阻放大器設計3dB頻寬為7GHz和增益為50dB而限制放大器3dB頻寬為10GHz和增益為50dB,總功率消耗為150mW與3.3V的供應電壓。
最後,設計一個3.125Gb/s應用於光纖接收的半速率時脈與資料回復電路,使用了延遲鎖定迴路和鎖相迴路技術。本電路使用TSMC 0.18-μm CMOS製程進行模擬,總功率消耗為50mW與1.8V的供應電壓。

In this thesis, we introduce the optical receiver components, including a transimpedance amplifier, a limiting amplifier, and a clock and data recovery circuit. Besides, these components were implemented in CMOS technology.
First, the CMOS limiting amplifier consists of a five-stage gain stage and a buffer for optical communication. In order to mitigate the bandwidth limitation of the amplifier, a bandwidth-extension technique with neutralized capacitors is adopted. Fabricated in a commercial 0.18-um CMOS process, the limiting amplifier provides gain of 45 dB and 3-dB bandwidth of 3.125 GHz, and consumes power dispassion 95 mW at 1.8-V supply voltage.
Secondly, a transimpedance amplifier and a limiting amplifier for 10Gb/s optical receiver with the design is proposed. The transimpedance amplifier is simulated in 0.35-µm SiGe process with a 3dB-bandwidth of 7 GHz and gain is 50dB. The limiting amplifier is simulated with a 3dB-bandwidth of 10 GHz and gain is 50dB, the power dissipation is about 150 mW from a 3.3-V supply.
Finally, a half rate clock and data recovery circuit for 3.125GHz optical receiver is proposed. This CDR circuit uses DLL and PLL technology. The CDR circuit is simulated in 0.18-um CMOS process, the power dissipation is about 50 mW from a 1.8-V supply.
其他識別: U0005-2208200713441000
Appears in Collections:電機工程學系所

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