Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7611
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dc.contributor楊榮吉zh_TW
dc.contributor林維亮zh_TW
dc.contributor.advisor楊清淵zh_TW
dc.contributor.author溫錦炘zh_TW
dc.contributor.authorWen, Jing-Shingen_US
dc.contributor.other中興大學zh_TW
dc.date2008zh_TW
dc.date.accessioned2014-06-06T06:40:15Z-
dc.date.available2014-06-06T06:40:15Z-
dc.identifierU0005-2208200714162000zh_TW
dc.identifier.citation參考文獻 [1] B.G. Goldberg, “Digital Techniques in Frequency Synthesis, McGraw-Hill, ”1999. [2] R.E. Best, “Phase-locked Loops: Design, Simulation and Application, ” McGraw-Hill,1998 [3] F.M. Garner, “Phaselock Techniques, ” 2nd ed , John wiley and Sons, NEW York,1979 [4] IEEE Std 802.11aTM-2003, “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5GHz Band.” [5] IEEE Std 802.11b-1999, “Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer Extension in the 2.4GHz Band.” [6] IEEE Std 802.11gTM-2003, “Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Further Higher Data Rate Extension in the 2.4GHz Band.” [7] J. Tierney, C.M. Rader ,and B. Gold, “ A Digital Frequency Synthesizer, ”IEEE Transcations. on Audio and Electroacoustics., Vol. AU-19 , NO.1, pp.48-57, Mar .1971 [8] P.O’Leary and F.Maloberti, “ A Direct-Digital Synthesizer With Improved Spectral Performance, ” IEEE Trans.Commum, Vol.39, NO.7, pp.1,046-1, 048, July 1991. [9] V.F Kroupa, V. Cizek, J. Stursa, and H. Svandova, “ Spurious Signals In Direct Digital Frequency Synthesizers Due To The Phase Truncation, ” IEEE Trans. Ultrason.,Ferroelect. Freq. Contr., Vol.47, NO.5, pp.1,166-1,172, Sept 2000. [10] F. Curticapean and J.Niittylahti, “Exact Analysis of Spurious Signals In Direct Digital Frequency Synthesizers Due to the Phase Truncation , ” Electron Lett., Vol.39, NO.6, pp.499-501, Mar 2003. [11] D.H.Guest, “Simplified Data-Transmission Channel Measurements, ” Hewlett-Packard J, Vol.26, NO.3, pp.15-24, Nov 1974. [12] D.A Sunderland, R.A Strauch, S.S Wharfield, H.T Peterson, and C.R Cole, “CMOS/SOS Frequency Synthesizer LSI Circuit For Spread Spectrum Communications , ” IEEE J.Solid-state Circuits, Vol SC-19, pp.497-505 , Aug 1984. [13] L.A.Weaver,and R.J.Kerr, “High Resolution Phase To Sine Amplitude Converter, ”U.S.Patent4,905,177,Feb,1990 [14] A. Bellaouar,et al , “Low-Power Direct Digital Frequency Synthesis For Wireless Communications , ” IEEE J.Solid-state Circuits, Vol 35, no. 3, pp.385-390 , Mar 2000. [15] J. E. Volder, “The CORDIC Trigonometric Computing Technique, ” IRE Trans. On Electron. Comput., EC-8:330-334, Sept. 1959. [16] J. S. Walther, “A Unified Algorithm for Elementary Functions,” in Proc. Spring Joint Computer Conference, pp. 379-385 , May 1971. [17] J. Vankka,K. Halonen, “Direct Digital Synthesizers: Theory, Design and Applications, ” Kluwer Academic Publisher,2001 [18] H.T Nicholas, III, H. Samueli, and B Kim, “The Optimization of Direct Digital Frequency Synthesizer Performance In The Presence of Finite Word Length Effects, ” in Proc. 42nd Annn. Frequency control Symp, pp357-363,June 1988. [19] J.F.Garvey and D.Babitch, “An Exact Spectral Analysis of A Number Controlled Oscillator Based Synthesizer, ” in proc. 44th Annu. Symp. Frequency control, 1999, pp 511-521. [20] L. Schuchman, “Dither Signals And Their Effect On Quantization Noise, ” IEEE Trans. Commun, Vol.12 ,no.4, pp.162-165 , 1964. [21] H.Spang, III and D.E Phillips, “Reduction of Quantizing Noise By Use of Feedback, ” IEEE Trans. Commun, Vol.10.no4, pp.373-380, 1962 [22] H Samueli, “Broadband Communications ICs: Enabling High-Bandwidth Connectivity In The Home And Office, ” in Proc. IEEE ISSCC, pp.26-30 , Feb, 1999 [23] D.A John and K. Martin, “Analog Integrated Circuit Design, ” John Wiley & Sons Inc.,1997 [24] R.van de Plassche, “Intergrated Analog-to-Digital and Digital-to Analog Converters, ”Kluwer Academic Publishers,1994. [25] Walt Kester, James Bryant, “Sample Data System , ” Analog Devices Inc. [26] Chi-H Lin, K.Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,"IEEE Journal of Solid-State Circuits,vol.33, pp.1948-1958, Dec. 1998. [27] K. Lakshmikumar et al., “Charracterrization and Modeling of Mismatch in MOS Transistors for Precision Analog Design , ” IEEE Journal of Solid-State Circuits,vol.21, pp.1057-1066, Dec. 1986 [28] Y. Cong and R. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoder DAC Arrays, ” IEEE Transcation on Circuit and Symtems II, vol.47,NO 7, pp.585-595, July. 2000 [29] T. Miki Y. Nakamura et al. , “A 80-MHz 8-b CMOS D/A Converter, ” IEEE Journal of Solid-State Circuits,vol.21, pp.983-988,Dec 1986. [30] M. M. Mano , “Digital Design 3rd edition, ”Prentice Hall, 2002 [31] R. Rogenmoser and Q. Huang, “An 800-MHz 1-um CMOS Pipelined 8-b Adder Using True Single-Phase Clocked Logic-Flip-Flops,” IEEE J. Solid-State Circuits, vol. 31, no. 3, March, 1996. [32] Q. Huang and R. Rogenmoser, “Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks,” IEEE J. Solid-State Circuits, vol. 31, no. 3, March, 1996. [33] B. Razavi, “Priciples of Data Conversion System Design,” IEEE Press, 1995. [34] S. Mortezapour and Edward K. F. Lee, “Design of Low –Power ROM-Less Direct Digital Frequency Synthesizer Using Nonlinear Digital-to-Analog Converter,”IEEE J. Solid-State Circuits, vol. 34, no. 10, Oct, 1999. [35] S. Mortezapour and E. Lee, “A Low Power Quadrature Direct Digital Frequency Synthesizer Using Nonlinear Resistor String DACs ,” in Proc. 24th Europ. Solid-State Circuits Conf., pp.348-351,Sept, 1998. [36] A.N. Mohieldin, A .Emira and E. Sanchez-Sinencio, “A 100-MHz 8-Mw ROM-Less Quadrature Direct Digital Frequency Synthesizer ,” IEEE J. Solid-State Circuits, vol. 37, no. 10, Oct, 2002 [37] J. Jiang and Edward K.F.Lee, “Segmented Sine Wave Digital –to –Analog Converters For Frequency Synthesizer ,” IEEE CICC Conf ,pp.165 – 168, May, 2001. [38] S. Mortezapour, and E. K. Lee, “Design of Low-Power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter,” IEEE J. Solid-state Circuits, vol. 34, no.10, Oct. 1999. [39] J, Jiang and E, K. Lee, “A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter,” IEEE Custom Integrated Circuits Conference , 2001 [40] E.S Vinck, “Analysis and Synthesis of Translinear Intergrated Circuits,” Elsevier Science Publisher B.V, 1988zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/7611-
dc.description.abstract頻率合成器大致可分為鎖相迴路及直接數位頻率合成器兩種結構形式,而本篇論文採用直接數位頻率合成器,也大致介紹直接數位頻率合成器的原理及不同架構的分別,最後也有提出異於傳統架構的兩個無記憶體式直接數位頻率合成器,第一架構是圍繞在非線性數位至類比轉換器上,因為我們將傳統式結構中的記憶體去除,改成以非線性數位至類比轉換器來實現,在考量到晶片實作上及整體效能的改進,進而將非線性數位至類比轉換器的架構改進成分段式數位至類比轉換器的架構,透過實驗證明了確實在效能上有所改進。儘管第一個晶片已經實現一個無記憶體的直接數位頻率合成器,我們又提出使用translinear的作法,這樣的作法也是一種無記憶體的實現方法,並且可以實現的特性是更加的好,而面積上比分段式非線性數位至類比轉換器的架構,可以省去龐大的微調數位控制電路,整體的特性更是進一步的提升,各方面來說都有很大的效果,唯獨製程的選擇是不得已。除此之外,此兩個晶片所使用的分段式數位至類比轉換器也是本論文的研究重點之一,因為整體架構我們除了節省面積之外,也朝向更高速的設計方式來實現直接數位頻率合成器,所以需要一個高速的數位至類比轉換器,論文中也有詳盡的去研究如何去設計出高速且高精確度的數位至類比轉器。 因此本篇論文將有三顆晶片實作驗證,第一顆晶片實作為一個每秒十億取樣率十位元的電流式CMOS數位類比轉換器研究,所使用的製程為0.18um CMOS,電路面積為1.4mm × 1.4mm,功率消耗約為131mW。量測結果可操作至850MHz,線性度INL、DNL皆在5LSB以下,THD量測值與理想值比較後,在高速率下皆在0.3%以下。而第二顆晶片為使用分段式數位至類比轉換器實現的直接數位頻率合成器的研究,但論文中的量測結果不佳,因此我們嘗試以不同的微調電路去重新實驗,同樣使用0.18um CMOS製程,電路面積為1.7mm × 1.6mm,功率消耗約為271mW。模擬結果電路可操作至1GHz,SFDR最高可達55dB。最後一顆晶片實作是利用translinear電路實現的直接數位頻率合成器,使用0.35um SiGe 製程,功率消耗約為205 mW,模擬結果電路可操作至500MHz,SFDR可達60 dB以上。zh_TW
dc.description.abstractThere are two kinds of frequency synthesizers include of phase lock loop based and direct digital frequency synthesizer (DDFS). In this thesis, direct digital frequency synthesizer is adopted and the principle of DDFS is introduced generally. Then, there are some comparisons about different structures. Finally, we propose two new structures different from conventional ones. The first one is major on non-linear digital to analog converter (DAC). To think about chip design and improve efficiency of all, we use segmented DAC to replace ROM of conventional ones. According to our experiment result, it prove the new structure can reach our goal. In the second one we propose an other new approach used translinear circuit with better performance. Compared with the first one, it can save the area which don’t use the fine tune decoder circuit and improve the over all efficiency. The only one drawback is the limitation of the technology. Besides, the DAC structure used in the two DDFS is an other important point of this thesis. When we design the all structure, we demand not only saving area but also more higher speed to out work. So we also have completed research about how to design a high speed DAC. Thus, there are three chips designed in this thesis. The first one is a research about 10bit 1GS/S Current-Steering DAC. The chip is implemented in 0.18um CMOS technology with the die area 1.4mm × 1.4mm and the power consumption is about 131mW. The measurement result of operation speed is up to 850MHz,and linearity INL、DNL are both under 5LSB. THD is measured under 0.3% in high speed operation. The second ones discussed a high-speed ROM-less direct digital frequency synthesizer realized by a segmented non-linear DAC. Because the measurement of this thesis is not good, we try another fine tune circuit to test again. The chip is implemented in 0.18um CMOS technology with the die area 1.7mm × 1.6mm and the power consumption is about 271mW. The measurement result of operation speed is up to 1GHz,and the maximum of SFDR is 55 dB. The last chip is a ROM-less direct digital frequency synthesizer realized by translinear circuit and implemented in 0.35um SiGe technology with power consumption is 205mW. The measurement result of operation speed is up to 500MHz,and SFDR is 60dB up .zh_TW
dc.description.tableofcontents目錄 誌謝 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i 摘要(中文) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ii 摘要(英文) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -iii 目錄 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iv 第一章 緒論 1.1 研究動機 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1.2 頻率合成器簡介及其應用- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1.3論文結構- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 第二章 直接數位頻率合成器 2.1 傳統式直接數位頻率合成器- - - - - - - - - - - - - - - - - - - - - - - - - - - - -3 2.1.1 直接數位頻率合成器原理- - - - - - - - - - - - - - - - - - - - - - - - - - - 4 2.1.2 傳統式直接數位頻率合成子電路介紹- - - - - - - - - - - - - - - - - - -5 2.1.3 直接數位頻率合成器雜訊分析- - - - - - - - - - - - - - - - - - - - - - - -7 2.2 直接數位頻率合成器之記憶體壓縮技巧- - - - - - - - - - - - - - - - - - - - 9 2.2.1 Quadrant Compression技巧 - - - - - - - - - - - - - - - - - - - - - - 9 2.2.2 Sunderland演算法- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 2.2.3 Taylor Series 演算法- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12 2.2.4 CORDIC演算法- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 2.2.5 各種演算法比較- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 2.3 直接數位頻率合成器之刺能削減(spur reduction)技巧- - - - - - - - -15 2.3.1 奇數(The odd-number)技巧- - - - - - - - - - - - - - - - - - - - - - - - 15 2.3.2 相位顫抖(Phase-Dithering)技巧- - - - - - - - - - - - - - - - - -15 2.3.3 Noise-Shaping 技巧- - - - - - - - - - - - - - - - - - - - - - - - - - - -16 第三章 數位至類比轉換器 3.1 數位至類比轉換器簡介- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 18 3.2 功能及規格介紹- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 19 3.2.1 數位至類比轉換器功能原理 - - - - - - - - - - - - - - - - - - - - - - 19 3.2.2 數位至類比轉換器規格簡介- - - - - - - - - - - - - - - - - - - - - - - - 19 3.3 數位至類比轉換器架構介紹- - - - - - - - - - - - - - - - - - - - - - - - - - - 24 3.3.1 電阻串列式(resistor string DAC) - - - - - - - - - - - - - - - - - - - - - 24 3.3.2 二進制權重電阻式(binary-weighted resistor DAC)- - - - - - - - - -25 3.3.3 電容切換式(switched-capacitor DAC) - - - - - - - - - - - - - - - - - 25 3.3.4 二進制碼電流源切換式(current mode binary-weighted code DAC)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 26 3.3.5 溫度計碼電流源切換式(current mode thermometer code DAC)- 27 3.4 每秒十億取樣率十位元電流式CMOS數位類比轉換器與內建三角波產生器研究- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -29 3.4.1 電路架構- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29 3.4.2 分段式DAC結構考量- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32 3.4.3 子電路介紹- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35 3.4.4 電路模擬- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 39 3.4.5 量測結果與結論- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 43 第四章 分段式數位至類比轉換器實現之無記憶體直接數位頻率合成器 4.1 簡介 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 47 4.2 電路架構與說明 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 4.2.1 粗調非線性數位至類比轉換器(coarse non-linear dac) - - - - - - 49 4.2.2 微調線性數位至類比轉換器(fine linear dac)- - - - - - - - - - - - - 50 4.3 數位至類比轉換器分段化依據- - - - - - - - - - - - - - - - - - - - - - - - - - 52 4.4 子電路介紹 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -52 4.4.1 ACC( Accumulator)累加器- - - - - - - - - - - - - - - - - - - - - - - - - - 52 4.4.2 Thermometer deocder電路- - - - - - - - - - - - - - - - - - - - - - - - - - 53 4.4.3 current source & switch電路- - - - - - - - - - - - - - - - - - - - - - - - 53 4.4.4 R_2R Binary weighted電路- - - - - - - - - - - - - - - - - - - - - - - - - -54 4.4.5 偏壓OP電路- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55 4.5 電路模擬- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55 4.5.1 spice模擬頻譜介紹- - - - - - - - - - - - - - - - - - - - - - - - - - 55 4.5.2 子電路模擬- - - - - - - - - - - - - - - - - - - - - - - - - - 57 4.5.3 Matlab行為模式模擬及Spices頻譜模擬- - - - - - - - - - - - - - - - 59 4.6 量測與結論- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 63 第五章 以Translinear電路實現之無記憶體直接數位頻率合成器 5.1 簡介 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 65 5.2 電路架構與說明 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 66 5.2.1 translinear電路介紹- - - - - - - - - - - - - - - - - - - - - - - - - - 66 5.2.2 translinear電路matlab模擬- - - - - - - - - - - - - - - - - - - - - - - - - -66 5.2.3 translinear電路spice模擬- - - - - - - - - - - - - - - - - - - - - - - - 69 5.2.4 dac電路介紹及其模擬- - - - - - - - - - - - - - - - - - - - - - - - - -70 5.3 電路模擬與規格比較 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 72 第六章 結論與未來展望 6.1 結論 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 73 6.2 未來展望 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 73 參考書目 參考文獻- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 76 附錄 ◎ Ching-Yuan Yang;Jing-Shing Wen, ” A High-Speed ROM-less Direct Digital Frequency Synthesizer Realized by a Segmented Non-linear DAC”, accepted by TENCON2007- - - - - - - - - - - - - - - - - - - - - - - - - - 79zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2208200714162000en_US
dc.subjectFrequency Synthesizeren_US
dc.subject頻率合成器zh_TW
dc.title無記憶體直接數位式頻率合成器之設計與分析zh_TW
dc.titleDesign and Analysis of ROM-Less Direct Digital Frequency Synthesizersen_US
dc.typeThesis and Dissertationzh_TW
item.languageiso639-1en_US-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
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