Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7615
標題: 應用於IEEE 802.11a/b/g之消除突波非整數頻率合成器
A Fractional-N Frequency Synthesizer with a Spur-Eliminated Topology for IEEE 802.11 a/b/g Channels
作者: 陳銘斌
Chen, Ming-Bin
關鍵字: synthesizer;頻率合成器;spur;突波
出版社: 電機工程學系所
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摘要: 
在本篇論文中,主要目的是利用一個多通道選擇的頻率合成器來實現本地振盪訊號,並能夠符合IEEE 802.11 a/b/g通道選擇的標準。並由於目前當下應用於頻率合成器之迴路濾波器大部分均使用電阻電容來組合而成,但在濾波器產生壓控振盪器控制電壓時會有漣波效應(ripple),而造成輸出頻率在頻譜產生參考頻率突波,會影響傳輸電路的效能表現。由此推論,去除電阻的濾波器可以有效抑制控制電壓的漣波效應,如此即可降低參考頻率突波,所以本論文以無電阻的鎖相迴路為基礎架構並做些許改進。另外在非整數的實現方面,相位補償技術是一種真實非整數除數鎖相迴路不同於一般常見的三角積分的平均式非整數鎖相迴路。此種技術能有效的改善量化誤差所造成的小數突波,此種技術需要週期相同但具有多個相位的訊號,而如何製造出補償相位是本技術的重點。
所以在頻率合成器的設計,可分為兩個主題。第一部分是使用可變電感架構的壓控振盪器來實現漣波抑制頻率合成器,其輸出頻率範圍4.6GHz~6.5GHz,並加上三角積分調變器進行調變,使其能夠達到除小數的功能,利用TSMC 0.18um標準CMOS製程做模擬,在1.8V電壓操作下功率消耗為75mW,晶片面積為1.4*1.4mm2。第二部分以上一個架構做基礎來實現消除突波技術,在此利用環型振盪器多相位輸出的優點,採取相位產生器和相位選擇器產生相位補償,以去除小數突波。而在環型振盪器中採用雙迴路的延遲迴路技術,用以提升振盪頻率,其輸出頻率範圍2.3GHz~2.6GHz,利用TSMC 0.18um標準CMOS製程做模擬,在1.8V電壓操作下功率消耗為65mW,晶片面積為0.815*0.66mm2。

In this thesis, the main purpose is to realize a LO signal with multi-channels frequency synthesizer for IEEE 802.11 a/b/g. On the instant, the loop filter in the frequency synthesizer is almost combined with the resisters and the capacitors. But, the VCO's controlled voltage is produced by loop filter and occurs the effect of ripple. This effect will generate reference spur in the spectra, and affect the performance of transmitter. For this reason, if we displace the resistor in the loop filter, it can suppress the effect of ripple in the VCO's controlled voltage. And then, the reference spur is decreased. So, we use the fundamental architecture of the no resistor frequency synthesizer to make some improvement in this thesis. In fractional part, phase-compensation fractional PLL is a different kind of true fractional PLL with averaging fractional PLL using D-S modulator architecture. This technique can minimum generating of quantization error which makes fractional spurs. The focus of the technique is how to generate the phase for compensation.
The work presents the frequency synthesizer based on PLLs. It divided into two parts of the work. The first one applies the inductive varactor voltage-controlled oscillator and delta-sigma modulator to realize a ripple-suppressed fractional-N frequency synthesizer. The output frequency range is from 4.6GHz to 6.5GHz. It is simulated by TSMC 0.18-um standard CMOS technology and power dissipation is about 75-mW under 1.8-V supply voltage. The chip area is 1.4*1.4mm2. The other one is to realized the spur-eliminated topology base on the last architecture of frequency synthesizer. Taking advantage of multi-phase generated by a ring oscillator, it adopts with a phase generator and a phase selector which generates phase compensation to reduce fractional spur. Because of the high speed operating, the ring oscillator is accepted with dual delayed loop technique. The output frequency range is from 2.3GHz to 2.6GHz. It is fabricated with a 0.18-um standard CMOS technology and power dissipation is about 65-mW under 1.8-V supply voltage. The chip area is 0.815*0.66mm2.
URI: http://hdl.handle.net/11455/7615
其他識別: U0005-2208200715012900
Appears in Collections:電機工程學系所

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