Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7658
標題: 以CPLD實現Delta-Sigma類比/數位轉換器
Implementation of a CPLD-Based Delta-Sigma Analog/Digital Converter
作者: 戴詩芃
Tai, Shih-Peng
關鍵字: CPLD;Delta-Sigma類比/數位轉換器
出版社: 電機工程學系
摘要: 
類比/數位轉換器在許多應用上扮演著舉足輕重的角色,其解析度與轉換時間將直接影響到整個系統的性能。大多數的類比/數位轉換器為達高解析度要求,對於電路元件有較嚴苛的限制,而Delta-Sigma類比/數位轉換器使用超取樣(oversampling)與雜訊整形(noise shape)的技術,主要的訊號轉換過程藉由數位訊號的計算完成,因此使類比電路的複雜性降低,且避免元件精確度的影響。
本論文以Altera EPF10K50SQC240-1 CPLD及運算放大器為主體,實現包含一階調變器、一位元量化器與三階間取濾波器的Delta-Sigma類比/數位轉換器,並以AT-MIO16XE-50資料擷取卡配合LabVIEW虛擬儀表軟體進行測試,測試結果顯示可有效的將輸入的類比訊號轉換為對應的數位訊號。

Analog-to-digital converter plays an important role in many applications, and its resolution and data conversion delay directly affects the performance of whole system. Most analog-to-digital converters require accurate electronic component to meet high-resolution demands, and cause them difficult to implement. However, Delta-Sigma analog-to-digital converters avoid the limit of electronic component and decrease the complexity of analog circuits because of using oversampling and noise shape technique to convert analog signal to digital signal.
This paper uses the Altera EPF10K50SQC240-1 CPLD and OP-AMP to implement a Delta-Sigma analog-to-digital converter, which includes a 1-order modulator, and 3-order decimation filter, and uses AT-MIO16XE-50 DAQ Card and LabVIEW visual instrument software to make an experiment test its performance. The result shows that the proposed circuit can convert analog signal to digital signal successfully.
URI: http://hdl.handle.net/11455/7658
Appears in Collections:電機工程學系所

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