Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7659
標題: 移動估計器與適用於MPEG-4之可逆式可變長度解碼器電路架構設計與實現
VLSI Architecture Design and Implementation of Motion Estimator and Reversible Variable Length Decoder for MPEG-4 Applications
作者: 黃寅瑞
Huang, Yin-Ruey
關鍵字: Full-Search Block-Matching Motion Estimation;全區域搜尋區塊比對演算法;Reversible Variable Length Coding;VLSI;可逆式可變長度編碼;超大型積體電路
出版社: 電機工程學系所
引用: [1] G. Agnew, “Digital video for the next millennium,” Video Development Initiative (ViDe), Tech. Rep., Apr. 1999. [2] B. G. Haskell, A. Puri, and A. N. Netravali, Digital Video: An Introduction to MPEG-2, ser. Digital Multimedia Standards. International Thomson Publishing, 1997. [3] Information Technology - Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbit/s - Part 2: Video, ISO/IEC 11172-2, 1993. [4] Information Technology - Generic Coding of Moving Pictures and Associated Audio Information: Video, ISO/IEC 13818-2 and ITU-T Recommendation H.262, 1996. [5] Video Codec for Audiovisual Services at p _ 64 Kbit/s, ITU-T Recommendation H.261, Mar. 1993. [6] Video Coding for Low Bit Rate Communication, ITU-T Recommendation H.263, Feb. 1998. [7] Information Technology - Coding of Audio-Visual Objects - Part 2: Visual, ISO/IEC 14496-2, 1999. [8] D. Wu, Y. T. Hou, W. Zhu, Y. Q. Zhang, and J. M. Peha, “Streaming video over the internet: Approaches and directions,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 3, pp. 282-300, Mar. 2001. [9] http://www.microsoft.com/windows/windowsmedia/default.aspx. [10] http://www.realnetworks.com/index.html. [11] http://www.apple.com/quicktime/index.html. [12] G. J. Conklin, G. S. Greenbaum, K. O. Lillevold, A. F. Lippman, and Y. A. Reznik, “Video coding for streaming media delivery on the internet,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 3, pp. 269-281, Mar. 2001. [13] J. G. Apostolopoulos,W. T. Tan, and S. J.Wee, “Video streaming: Concepts, algorithms, and systems,” HP, Tech. Rep. HPL-2002-260, Sept. 2002. [14] B. J. Shieh, Y. S. Lee, and C. Y. Lee, “A new approach of group-based VLC codec system with full table programmability,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 2, pp. 210-221, Feb. 2001. [15] A. Mukherjee, N. Ranganathan, and M. Bassiouni, “Efficient VLSI designs for data transformation of tree-based codes,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 38, no. 3, pp. 306-314, Mar. 1991. [16] Y. Ooi, A. Taniguchi, and S. Demura, “A 162 Mbit/s variable length decoding circuit using an adaptive tree search technique,” in Proc. CICC'94, May 1994, pp. 107-110. [17] S. M. Lei and M. T. Sun, “An entropy coding system for digital HDTV applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 1, no. 1, pp. 147-155, Mar. 1991. [18] E. Komoto and M. Seguchi, “A 110 MHz MPEG2 variable length decoder LSI,” in Proc. 1994 IEEE Symp. VLSI Circuits, 1994, pp. 71-72. [19] S. Malloy and R. Jain, “Low power VLSI architectures for variable length encoding and decoding,” in IEEE Proc. 40th Midwest Symp. Circuits Syst., 1997, pp. 997-1000. [20] M. Novell and S. Malloy, “VLSI implementation of a reversible variable length encoder/decoder,” in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 4, 1999, pp. 1969-1972. [21] S. H. Cho, T. Xanthopoulos, and A. P. Chandrakasan, “A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 6, pp. 249-257, Jun. 1999. [22] S. W. Lee and I. C. Park, “A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords,” IEEE Trans. Circuits Systems II, Analog Digit. Signal Process., vol. 50, no. 2, pp. 73-82, Feb. 2003. [23] H. Park and V. K. Prasanna, “Area efficient VLSI architectures for huffman coding,” IEEE Trans. Circuits Systems II, Analog Digit. Signal Process., vol. 40, no. 9, pp. 568-575, Apr. 1993. [24] J. Nikara, S. Vassiliadis, J. Takala, and P. Liuha, “Multiple-symbol parallel decoding for variable length codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 7, pp. 676-685, Jul. 2004. [25] C. H. Liu, B. J. Shieh, and C. Y. Lee, “A low-power group-based VLD design,” in Proc. ISCAS'04, May 2004, pp. 337-340. [26] C. Fogg, “Survey of software and hardware VLC architectures,” SPIE Image and Video Compression Conf., vol. 2186, pp. 29-37, 1994. [27] Jennifer L. H. Webb, “Efficient table access for reversible variable length decoding,” IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 8, pp. 981-985, Aug. 2001. [28] Chujoh T, Watanabe T. Reversible variable length codes and their error detecting capacity. Proceedings of the Picture Coding Symposium, Portland, OR, 1999. p. 341-4. [29] Schalkwijk JPM. An algorithm for source coding. IEEE Transactions on Information Theory 1972;18:395-9. [30] M.Keating and P. Bricaud, Reuse Methodology Manual, 3rd ed. Norwell, MA: Kluwer, 2002. [31] Tsung-Han Tsai, Wen-Cheng Chen, and Chun-Nan Liu, “A low power VLSI implementation for variable length decoder in MPEG-1 layer III,” in Proc. IEEE Int. Conf. Multimedia and Expo., vol. 1, pp. I-133-6, July 2003. [32] K. M. Yang, M. T. Sun, and L. Wu, “A family of VLSI designs for the motion compensation block-matching algorithm,” IEEE Transactions on Circuits and Systems., vol. 36, no. 10, pp. 1317-1325, Oct. 1999. [33] L. De Vos and M. Stegherr, “Parameterizable VLSI architectures for the full-search block-matching algorithm,” IEEE Transactions on Circuits and Systems., vol. 36, no. 10, pp. 1309-1316, Oct. 1989. [34] C. H. Hsieh and T. P. Lin, “VLSI architecture for block-matching motion estimation algorithm,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 2, no. 2, pp. 169-175, June 1992. [35] T. Komarek and P. Pirsch, “Arrary architectures for block matching algorithms,” IEEE Transactions on Circuits and Systems., vol. 36, no. 10, pp. 1301-1308, Oct. 1989. [36] H. Yeo and Y. H. Hu, “A novel modular systolic array architecture for full-search block matching motion estimation,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 5, no. 5, pp. 407-416, Oct. 1995. [37] Y. K. Lai and L. G. Chen, “A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 8, no. 2, pp. 124-127, April 1998. [38] S. Kittitornkun, and Yu Hen Hu, “Frame-level pipelined motion estimation array processor,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 11, no. 2, pp. 248-251, Feb. 2001. [39] N. Roma, and L. Sousa, “Efficient and configurable full-search block-matching processors,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 12, no. 12, pp. 1160-1167, Dec. 2002. [40] Yeong-Kang Lai, and Lien-Fei Chen, “A high data-reuse architecture with double-slice processing for full-search block-matching algorithm,” IEEE International Symposium on Circuits and Systems., vol.2 pp. 716-719, May. 2003. [41] J. C. Tuan, T. S. Chang, and C. W. Jen, “On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 12, no. 1, pp. 61-72, Jan. 2002. [42] M. J. Chen, L. G. Chen, K. N. Cheng, and M. C. Chen, “Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithm,” IEE Proc.-Vis. Image Signal Process., vol. 143, pp. 217-222, Aug. 1996. [43] Y. K. Lai, L. G. Chen, T. H. Tsai, and P. C. Wu, “A novel scalable architecture with memory interleaving organization for full search block-matching algorithm,” IEEE International Symposium on Circuits and Systems., vol. 2, pp. 1229-1232, June 1997. [44] C. Y. Chen, C. T. Huang, Y. H. Chen, and L. G. Chen, “Level C+ Data Reuse Scheme for Motion Estimation with Corresponding Coding Order,” IEEE Transactions on Circuits and Systems for Video Technology., vol. 16, no. 4, pp. 553-558, April 2006.
摘要: 
可變長度編碼(variable length coding)是一個被廣泛使用在數位視訊壓縮系統的技術,它能提供有效率的資料壓縮而廣為人知,但是在有雜訊的環境下卻容易受影響。由於可攜式多媒體應用的需求增加,使得功率消耗在一個可攜式多媒體系統中成為一個非常重要的因素。同時,視訊資料在透過有雜訊的通道做資料交換時容易產生錯誤,ITU H.263+與ISO MPEG-4視訊壓縮標準紛紛提出具有較好容錯性(error resilient)的可逆式可變長度編碼(reversible variable length coding)。在本論文中,我們介紹一個全新、適用於MPEG-4的可逆式可變長度編碼的解碼方法。因為使用可逆式可變長度編碼的字碼結構較特別,一般用來解可變長度編碼的解碼技術用在可逆式可變長度編碼上時變得非常沒有效率。這個新的方法使用簡單的邏輯運算即能快速判斷出字碼的長度並且做解碼的動作,同時也容易以硬體的方式實現。我們也提出了以此新方法為基礎的硬體架構,這個架構使用上述的新方法與查表分割(table partitioning)技術。經過實作後的結果,證明了我們提出的架構與其他架構相較之下,能夠在不犧牲效能的前提下達到低功率的需求。此電路使用標準單元以及TSMC 0.18um 1P6M製程實作。晶片實作結果顯示本架構可以工作於100MHz,其功率消耗為4.969 mW,晶片面積為1.006×1.006 mm2。
另一方面,由於高效能以及高解析度視訊品質的需求日益漸增,記憶體的頻寬與處理能力也逐漸引起視訊系統設計者的注意。在本論文中,我們亦提出了一個適用於全區域搜尋區塊比對演算法(full-search block-matching algorithm),且具有可調性以及管線化的二維移動估計器架構。這個提出的二維移動估計器架構在畫面的邊界時仍然能夠平順地處理連續不同畫面間的資料,而不會有任何的處理閒置時間。除此之外,我們也提出了一個可調式(scalable)的架構來滿足處理能力的需求,並且使用層級C+的資料重複使用來降低外部記憶體頻寬。實作結果顯示,我們提出的架構可以完成畫面層級(frame-level)且百分之百的全管線化(pipelined)運算,並且能夠針對不同的視訊應用達到以效能為驅策(performance-driven)的需求。此電路目前已經使用標準單元以及TSMC 0.18um 1P6M製程實作。晶片實作結果顯示本架構可工作於100MHz以及其消耗功率為365.135 mW,晶片面積為3.352×3.352 mm2。

Variable length coding (VLC) is a widely used technique in digital video compression systems. It is known for its efficient compression, but is susceptible to noisy environments. Due to the increased demand for portable multimedia systems has made power consumption a very important factor. Current ITU H.263+ and ISO MPEG-4 standards have used reversible variable length coding (RVLC) which provides greater error robustness than non-reversible counterparts (VLC) due to the growing need for wireless exchange of compressed image and video signals over noisy channels. In this thesis, a new method for RVLC decoding is described. Since the special structure of RVLC codewords, the decoding techniques that are common for regular VLC are less efficient when used with RVLC. The new method uses simple logical operations to determine the length of codewords quickly, and then codewords are decoded. It is easily implemented with hardware, we proposed a VLSI architecture based on this new method and the architecture also uses the technique of table partitioning. The experimental result shows that our architecture can achieve lower power consumption without sacrificing performance than others. The proposed architecture has been implemented using standard cell methodology for TSMC 0.18um 1P6M technology. The chip implementation results show that proposed architecture can work at 100MHz and its power consumption is about 4.969 mW. The chip size is 1.0061.006 mm2.
Besides, owing to the video qualities of high performance and high resolution, the memory bandwidth and throughput come into video system designer notice. In the thesis, a scalable two-dimensional pipelined motion estimation processor for full-search block-matching algorithm (FSBMA) is also proposed. The proposed 2-D motion estimation processor can perform the pixels of the consecutive frames smoothly without any processor idle time at frame boundaries. Moreover, we propose a scalable architecture to satisfy the requirements of the throughput, and further, to reduce the external memory bandwidth with level C+ data reuse. The experimental result shows that our architecture can accomplish frame-level 100% fully pipelined computation and achieve the performance driven requirements for different video applications. The proposed architecture has been implemented using standard cell methodology for TSMC 0.18um 1P6M technology. The chip implementation results show that proposed architecture can work at 100MHz and its power consumption is about 365.135 mW. The chip size is 3.3523.352 mm2.
URI: http://hdl.handle.net/11455/7659
其他識別: U0005-2308200714270300
Appears in Collections:電機工程學系所

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