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標題: 應用於無線區域網路接收機之射頻前端電路
The RF Front End for WLAN Receiver
作者: 黃俊傑
關鍵字: CMOS;無線區域網路;WLAN;IEEE 802.11 b/g;current reuse;LNA;Subharmonic Mixer;Noise figure;Control Gain;低雜訊放大器;次諧波混波器;可調式增益
出版社: 電機工程學系所
引用: Reference [1] Behzad Razavi, “ RF MICROELECTRONICS” 1998 Prentice Hall PTR Upper Saddle River NJ 07458 [2] Thomas H. Lee “The DESIGN OF CMOS RADIO-FREQUENCY INTEGRATED CIRCUITS” Cambridge University Press 1998 [3] Reinhold Ludwig, and Pavel Bretchko, “RF Circuit Design Theory and Applications” 2000 Pearson Education International Upper Saddle River NJ 07458 [4] David M. Pozar, “Microwave Engineering Third Edition” 2005 John Wiley & Sons, Inc. [5] “Thermal Agitation of Electricity in Conductors,” Phys. Rev., v.32 July 1928, pp. 97-109 [6] “Thermal Agitation of Electric Charge in Conductors,” Phys. Rev., v32 July 1928, pp. 110-13 [7] Annalen der Physik, “Uber spontane Stromschwankungen in verschiedenen Electrizitatsleitern” [“On Spontaneous Current Fluctuations in Various Electrical Conductors”], v.57, 1918, pp.541-67 [8] H. T. Friis, “Noise Figure of Radio Receiver,” Proc. IRE, vol.32, pp.419-422, July 1944. [9] D. K. Shaeffer, and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifer”, IEEE J. Soild-State Circuits, Vol. 32, No. 5, May 1997 [10] M. L. Edwards, and J. H. Sinksy, “A New Criteria for Linear 2-Port Stability Using a Single Geometrically Derived Parameter,” IEEE Trans. Microwave Theory and Techniques, vol. MTT-40, pp.2803-2811, December 1992 [11] Behzad Razavi, “Design of Analog CMOS Integrated Circuits” McGraw-Hill, Inc. International Edition 2001 [12] Francesco Gatta, Enrico Sacchi, Francesco Svelto, Paolo Vilmercati, and Rinaldo Castello, “A 2-dB Noise Figure 900-MHz Differential CMOS LNA,” IEEE Journal of solid-state circuits, vol36, NO.10, October 2001 [13] A. N. Karanicolas, “A 2.7-V 900-Mhz CMOS LNA and Mixer,” IEEE Journal of solid-state circuits, vol.31, December 1996 [14] B. Gilbert, “A precise four quadrant multiplier with sub-nanosecond response,” IEEE Journal of solid-state circuits, vol. SC-3, pp. 365–373, December 1968 [15] Marc Goldfarb, Ed Balboni, and John Cavey, “Even Harmonic Double -Balanced Active Mixer for Use in Direct Conversion Receivers,” IEEE Journal of solid-state circuits, vol.38, NO.10, October 2003 [16 ] B. Floyd, J. Metha, C. Gamero, and K. O, “A 900-MHz 0.8-_m CMOS low noise amplifier with 1.2-dB noise figure,” in Proc. Custom Integrated Circuits Conf., May 1999, pp. 661–664 [17] G. Gramegna, A. Magazzù, C. Sclafani, and M. Paparo, “Ultra-wide dynamic range 1.75-dB noise figure 900-MHz CMOS LNA,” in Proc. Int. Solid–State Circuits Conf., Feb. 2000, pp. 380–381 [18] Q. Huang, P. Orsatti, and F. Piazza, “GSM transceiver front-end circuits in 0.25-_m CMOS,” IEEE Journal of solid-state circuits, vol. 34, pp. 292–303,Mar. 1999 [19] K. Itoh et al., “A 2 GHz band even harmonic type direct conversion receiver for W-CDMA mobile terminal utilization,” in IEEE Int. Microwave Symp. MTT-S Dig., June 2000, pp. 1957–1960 [20] M. Shimozawa et al., “A passive-type even harmonic quadrature mixer using simple filter configuration for direct conversion receiver,” in IEEE Int. Microwave Symp. MTT-S Dig., June 2000, pp. 517–520 [21] K. Itoh et al., “Even harmonic type direct conversion receiver ICs for mobile handsets: Design challenges and solutions,” in IEEE Radio Frequency Integrated Circuits (RFIC) Symp. Dig. Papers, June 1999, pp.53–56 [22] T. Yamaji et al., “An I/Q active balanced harmonic mixer with IM2 cancellers and a 45 degree phase shifter,” IEEE Journal of solid-state circuits, vol.33, pp. 2240–2246, Dec. 1998 [23] CIC 訓練課程, “Design of RF CMOS IC,” 上課講義 [24] 中興大學 “射頻積體電路” 上課講義
所以本篇論文主要研究於IEEE 802.11 b/g的無線網路接收機部分,內容主要包含高頻積體電路理論、低雜訊放大器、混波器,使用 TSMC 0.18um 1P6M CMOS製程。低雜訊放大器部份透過電路技巧使用了current reuse的架構,可以在相同的功率消耗之下,能有比較好的效能,另外還設計了可以調整增益的機制在裡面,透過電壓或電流偏壓的控制,可以改變電路本身的特性。混波器採用了次諧波混波器(Subharmonic Mixer),這種架構應用於直接降頻架構可以減少DC Offset的現象,而且也設計了一個控制輸出電壓的機制,它不僅可以維持輸出電壓的準位,而且還可以透過它控制混波器的增益以及線性度。

This thesis major study in IEEE 802.11 b/g for WLNA Receiver . The contents include RF Fundamental, Low Noise Amplifier(LNA),and Mixer.
We use the TSMC 0.18um 1P6M CMOS process to implement our circuit.
The low noise amplifier uses the technology called current reuse. Since PMOS devices in scaled technology, the idea is to realize the input stage shunting an inductively degeneration NMOS stage with a PMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Besides the current reuse, we utilize control gain to change current or voltage. Thus, it can change the circuit's performance.
A active double-balance even harmonic mixer is introduced. This architecture can avoid the problem of DC Offset in direct conversion. It not only haves the control gain to keep the voltage of output circuit, but also can vary gain and linearity of the mixer.
其他識別: U0005-2308200716010500
Appears in Collections:電機工程學系所

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