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標題: 高速及低功率之新型雙緣觸發正反器
A New High-speed and Low-power Double Edge-Triggered D Flip-Flop
作者: 王硯昭
Wang, Yen Chao
關鍵字: low power;低功率;prescaler;Flip-Flop;DETFF;High Speed;PLL;Latch;Wireless LAN;預除器;正反器;雙緣觸發正反器;高速;頻率合成器;資料栓鎖;IEEE802.11a
出版社: 電機工程學系
本篇論文研究一個高速及低功率之新型雙緣觸發正反器(Double Edge Triggered Data Flip Flop, DETFF)架構與電路設計,所提出的電路分兩部份,分別是4T/6T的雙脈衝產生器及一個獨立的新型雙脈衝資料栓鎖。所提出的新型雙脈衝資料栓鎖(Dual Pulse Data Latch, DPDL)只有使用6個電晶體。而所提出的兩組雙脈衝產生器只有使用4個及6個電晶體,並可以提供給數個DPDL使用,以達到更省電的效果。
本架構之新型雙緣觸發正反器架使用的是TSMC 0.18um 1P6M的製程,操作電壓0.6~2.0V。模擬結果顯示,在2.0V、1.8V及0.6V的電源供應下分別可達到2.3GHz、2.0GHz及83.33MHz的操作速度,並分別消耗了945uW、675uW及1.88uW的功率。此外,將新提出的DPDL應用於除頻器電路中,模擬結果顯示,此除2電路,在2.0V、1.8V及0.5V的電源供應下工作頻率為6.00GHz、5.26GHz及23.2MHz使用了219.5uW、162.8uW及46nW的功率。

In this thesis, a new high-speed and low-power CMOS double-edge-Triggered D flip-flop (DETDFF) is proposed. It consists of two parts. One is 4T/6T dual pulse generator and another one is a dual pulse data latch. The proposed Dual Pulse Data Latch (DPDL) uses and as the trigger signals to latch. The DPDL uses only six transistors with 2 transistor be clocked. Otherwise, A separate and for a trigger signal to the DPDL is used, the DPDL is suitable for the design of the divider and prescaler circuits.
The DETFF is designed by using the TSMC 0.18um single poly six metal CMOS technology. The HSPICE simulation results show that the operating speed and the power consumption of the DETDFF are 2.3GHz and 945uW, 2.0GHz and 675uW, and 83.33MHz and 1.88uW when the supply voltage of 2.0V, 1.8V and 0.6V, respectively.
Moreover, the proposed DPDL can be applied in the frequency divider circuit. Simulation results show that the operating speed and the power consumption of the divided—by-2 circuit are 6.0GHz and 219.5uW, 5.26GHz and 162uW, and 23.2MHz and 46uW under the supply voltage of 2.0V, 1.8V, and 0.5V, respectively. Therefore, the proposed circuits are very suitable for low-power and high-speed CMOS VLSI applications
Appears in Collections:電機工程學系所

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