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標題: 適用於嵌入式系統單晶片之同步動態記憶體控制器矽智產設計與驗證
Design and Verification of the SDRAM Controller IP for Embedded System on Chip
作者: 王建智
關鍵字: Embedded Systems-on-Chip;嵌入式系統單晶片;SDRAM Controller;Intellectual Property;Memory Access Optimization;AMBA;Functional Verification;e verification Language;eVC;同步動態記憶體控制器;矽智產;記憶體存取最佳化;高等微處理器匯流排架構;功能驗證;e 驗證語言;e 驗證元件
出版社: 電機工程學系
隨著積體電路製程能力的提昇,加上後PC市場時代的來臨,全球半導體產業已明顯走往嵌入式系統單晶片 (Embedded System on Chip)的設計趨勢。然而在一個嵌入式系統單晶片中,影響速度與效能的關鍵因素,除了須審慎設計系統架構之外;由於晶片內之動態記憶體控制器必須時時承受如主要微處理器 ( Host Processor )、數位訊號處理器(Digital Signal Processor, DSP)、直接記憶體存取(Direct Memory Access, DMA)控制器等高速IP大流量資料存取,故亦為影響速度與效能之重要關鍵。在本論文裡,將探討嵌入式系統單晶片使用記憶體的問題,並討論與分析同步動態記憶體(Synchronize DRAM;SDRAM)的標準架構與特性,進而設計出具AMBA 2.0標準晶片匯流排介面且符合矽智財品質規範(IP Qualification Guidelines)之高效能SDRAM控制器IP,此IP之功能驗證則依e驗證方法論,設計e語言驗證程式,在完整的驗證環境中執行。最後採用UMC 0.18mm CMOS 製程於符合100MHz的操作頻率條件下合成整個電路,並完成實體驗證。

Apparently, especially in post-PC era, the semiconductor industry has tried to make embedded System-on-Chip become reality after the CMOS process technologies have been significantly improved. However, to process a well designed embedded SoC is definitely not a commonplace. In most cases, there are indications that one of the major factors to influence performance of a well designed SoC is the SDRAM controller. Frequent access form a host processor, a digital signal processor and a direct memory access controller will cause a giant data flow into the SDRAM controller back and forth. That will halt the system for a while.
In this thesis, memory utilization of SoC and a standard architecture and characteristics of SDRAM will be investigated. Based on the analyses above, a high-performance SDRAM controller IP, which complies with AMBA 2.0 specification and IP Qualification guidelines, can be designed. An e language will be employed to verify the SDRAM controller IP under a pre-defined AHB eVC environment. This IP is also synthesized by using UMC 0.18um CMOS technology.
Appears in Collections:電機工程學系所

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