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標題: 無線通訊頻率合成器電路設計與實作
Design and Implementation of Frequency Synthesizer Circuitry for Wireless Communication
作者: 李紹宇
Li, Shao-Yu
關鍵字: Frequency Synthesizer;頻率合成器;Prescaler;前置除頻器
出版社: 電機工程學系
近年來無線通訊產業發展快速,元件製造技術日趨成熟,使得整合數位、類比電路實現單晶片系統整合(SoC)的理想不再遙不可及,伴隨而來的新挑戰即為晶片內最難處理的時脈問題,其中包含了時脈同步和錯斜修正以及時脈調變等技術,都必更跟上晶片演進的步伐;有鑑於此,各架構之鎖相迴路應聲成為電路設計中主流焦點,且高精確度及多頻道切換功能之頻率合成技術亦廣泛被業界採用。本篇論文參考IEEE 802.11b/g標準規格,因應無線通訊系統要求的高線性度、高工作頻率去設計符合2.4GHz ISM頻帶之射頻前端電路中一關鍵組件∼頻率合成器;並於台積電(TSMC 0.35um CMOS 2P4M)所提供之製程技術完成晶片,再以NDL高頻量測實驗室提供的On-wafer量測完成實作之量測。論文中分別描述三個規格不同之高速前置除頻器,主體電路架構皆由CML Master-Slave DFF所組成,其中包括1.5GHz之除二電路、2.4GHz之除四除五電路以及2.4GHz之多模除頻電路(除數可從256到271,共15個通道)。論文最後再提出一個2.4GHz整數N多通道頻率合成器電路之設計模擬及下線實作。

For the wireless communication industry developing rapidly in recent years, the component manufacturing technology becomes ripe for integrating analog and digital circuits to realize system on a chip (SoC) no longer out of reach. The following new challenge is the clock problems inside the chip, including clock synchronization, deskew issue, and frequency modulation etc. In view of this, all kinds of phase-locked loops circuits become the major focus in the circuit design, and high accuracy and multi-channel synthesizer are adopted by the industry extensively. In this thesis, we discuss the circuit chips' design of frequency synthesizer which meets the need of the IEEE 802.11b/g standard specification for the RF Front-end environment. All chips are implemented by the TSMC's 2P4M, 0.35um CMOS technology, and measured by the On-wafer techniques which provided by the NDL's RF group.
Moreover, we provide three different topologies of high speed Prescaler all constructed by Current Mode Logic Master-Slave DFF circuits , including 1.5 GHz Prescaler (divided-by-2), 2.4 GHz Prescaler (divided-by-4/5), and 2.4 GHz multi-modulus Prescaler ( divided-by-256~271). Finally, we propose a 2.4 GHz integer N multi-channel frequency synthesizer.
Appears in Collections:電機工程學系所

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