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|標題:||IEEE 802.11a 無線區域網路之載波回復電路
Carrier recovery circuit in IEEE 802.11a WLAN
在本論文中我們主要討論頻率及相位漂移對IEEE 802.11a基頻接收機所造成的影響，在IEEE所制定的IEEE 802.11a協定中規定，它的中心頻率是在5GHz這個頻段，而整個系統可容許的頻率偏差是+/- 20 ppm，也就是+/- 100 KHz，因此我們採用載波回復電路來移除介於傳輸信號及接收信號之間的頻率偏差，並修正接收信號的相位錯誤。整個載波回復電路使用Verlilog來模擬整體電路功能，而所合成出來的面積是43563個電晶體數，晶片大小約為2.6 mm x 2.6mm。
Due to the growth of the electronic technology, the computer's capability is upgraded and the transfer of information has become more and more important. The Wireless Local Area Network (WLAN) is a very popular technology for information transmission. However, the wireless network systems is transferred by the air and it would be degraded by a lot of factors including channel fading, ISI, frequency offset, phase offset, etc. To deal with these problem, it is necessary to design components such as Timing Recovery, Carrier Recovery Circuit, Equalizer, etc.
In this thesis, we discuss the effects of the frequency offset and the phase offset in IEEE 802.11a baseband receiver. According to the standard specifies, its central frequency is in the 5 GHz band, and the frequency offset tolerance is +/- 20 ppm. So, the whole system has +/- 100 KHz frequency tolerance. Here, we utilize a carrier recovery circuit to remove the frequency offset between the transmitter and the receiver and to correct the phase offset of the received signal. The whole carrier recovery circuit was described in Verilog HDL code and synthesized using 0.35um 2p4m cell library. The gate counts are 43653 and the chip size is 2.6mm * 2.6mm.
|Appears in Collections:||電機工程學系所|
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