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標題: 多相位輸出延遲鎖定迴路的分析與設計
Analysis and Design of a Multiphase-Output Delay-Locked Loop
作者: 黃柏仁
Huang, Po-Jen
關鍵字: delay-locked loop;延遲鎖定迴路;multiphase;resetable D-flip-flop;locking problem;多相位;可重置之動態D型正反器;鎖定問題
出版社: 電機工程學系

In this thesis, a multiphase-output delay-locked loop (DLL) is presented. In the proposed multiphase-output DLL, the start-controlled phase/frequency detector (PFD) is used to provide precise multiphase-output without the locking problem. The PFD utilizes a new NAND-resetable dynamic DFF so that a shorter reset path is achieved. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate in lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated by using the TSMC 0.35-um DPQM CMOS process. The measurement results show that the total delay time between the input and the output of the experimental multiphase-output DLL is just one clock cycle and all of the delay elements provide precise multiphase-output without the harmonic locking or the false locking problem. The power consumption of the experimental multiphase-output DLL is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can be supplied from 1.5 V to 2.5 V without improper function. The active area is 426 um X 381 um.
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