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標題: 適用於低跨壓之元件新型雙幫浦電路
The New Dual Pumping Circuits for Low Voltage Drop Devices
作者: 汪政鴻
Wang, Zheng-Hong
關鍵字: Dual Pumping Circuits;雙幫浦電路
出版社: 電機工程學系
摘 要
本論文中,我們在雙分支的架構下使用一個特殊基極連接技術能有效的降低基體效應和避免p-n 接面順偏導通之漏電現象,此電荷幫浦電路能使用在台積電0.18微米的CMOS元件製程技術操作於低電壓,另一個重要的特點就是要使每一級輸出能達到更穩定的電壓值,目的是為了使電晶體的閘極到源極或汲極壓差小於5.6伏特,分別在供應電壓從2.6到3.7伏特之間,此外加入一個大振幅時脈訊號產生電路用來供給主要電晶體閘級連接的電容,以增加在低電壓操作時電晶體傳導電荷的能力,可操作於2伏特以下的低電壓,另外相較於傳統單分支的架構,在雙分支的架構下也能提供較穩定的輸出電流,使用4級的正或負電荷幫浦電路可以產生高達8.5或-7伏特的輸出電壓在供應電壓為1.8伏特。

Recently, low-voltage low power consumption integrated circuits become popular due to battery-powered portable storage equipment. For example, flash memories have been utilized in handheld digital equipment such as personal cell phones and digital cameras. However, programming or erasing the Flash cells needs very high positive or negative voltages. Therefore, efficient pumping circuits are very critical to achieve this goal.
We employed dual-branch with a special substrate connection technique to eliminate the body effect and avoid p-n junction forward major conduction. Due to the low voltage operation of 0.18m CMOS devices, another important feature is to maintain the output of each stage to be a more stable voltage value in order to make transistors gate to source or to drain voltage drop less than 5.6V, respectively for supply voltage of from 2.6V to 3.7V. However, the high voltage clock circuit may be to boost the clock amplitude applied to the gate of the main pass transistor to increase the charge transfer capability of the MOS transistors under low supply voltages, such as 2V or below. In addition, the two-branch structure also provides more stable output loading current than the conventional one branch structure. The simulation results show the boosted voltage could reach 8.5V and -7V at supply voltage 1.8V using 4-stage positive and negative pumps
Appears in Collections:電機工程學系所

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