Please use this identifier to cite or link to this item:
Study on low loss transmission line and wideband low noise amplifier
|關鍵字:||CPW;共平面波導;LNA;CMOS;millimeter wave;UWB;低雜訊放大器;CMOS;毫米波;超寬頻||出版社:||電機工程學系所||引用:||B. Heydari, M. Bohsali, E. Adabi, and A.M. Niknejad, “Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS,” IEEE J. of Solid-State Circuits, Vol. 42, pp. 2893-2903, Dec., 2007. H. Hasegawa, M. Furukawa, and Yanai H., “Properties of Microstrip Line on Si-SiO2 System,” IEEE Trans. Microwave Theory and Techniques, Vol. 19, pp.869-881, Nov., 1971. S. Zaage, E. Groteluschen, “Characterization of the broadband transmission behavior of interconnections on silicon substrates,” IEEE Trans. Components, Hybrids, and Manufacturing Technology, Vol. 16, pp. 686-691, Nov., 1993. B. Kleveland, C.H. Diaz, D. Vook, L. Madden, T.H. Lee, and S.S. Wong, “Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design,” IEEE J. of Solid-State Circuits, Vol. 36, pp. 1480-1488, Oct., 2001. S. Seki, and H. Hasegawa, “Cross-tie slow-wave coplanar waveguide on semi-insulating GaAs substrates,” Electronics Letters, Vol. 17, pp. 940-941, Dec., 1981. I.C.H. Lai, and M. Fujishima, “High-Q Slow-Wave Transmission Line for Chip Area Reduction on Advanced CMOS Processes” IEEE International Conf. of Microelectronic Test Structures, pp. 192-195, Mar., 2007. Jaewon Kim, Byunghoo Jung, Philip Cheung, and Ramesh Harjani, “Novel CMOS Low-loss Transmission Line Structure” IEEE International Conf. of Radio and Wireless, pp. 235-238, Sept., 2004. Juin-Wei Huang, Chao-Shiun Wang, Chorng-Kuang Wang, and Shih-Huang Yeh, “Vertical-Ground-Plane Transmission Lines for Miniaturized Silicon-Based MMICs” in IEEE Radio Frequency integrated Circuits (RFIC) Symposium, pp.563-566, June 2007. T.S.D. Cheung, and J. R. Long, “Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits,” IEEE J. of Solid-State Circuits, Vol. 41, pp. 1183-1200, May, 2006. Agilent momentum. (http ://www.agilent.com) W.R. Eisenstadt, and Y. Eo, “S-parameter-based IC interconnect transmission line characterization,” IEEE Trans. Components, Hybrids, and Manufacturing Technology, Vol. 15, pp.483-490, Aug., 1992. David M. Pozar, Microwave Engineering, 2nd ed. Wiley, Sept., 2004. Ansoft HFSS.( http://www.ansoft.com) Agilent Advanced Design System. (http://www.agilent.com) K.C. Gupta, R. Garg, I. Bahl, and P. Bhartia, Microstrip lines and slotlines, Artech House Publishers, Mar., 1996. P. J. van Wijnen et al., “A new straightforward calibration and correction procedure for “on-wafer” high-frequency S- parameter measurements (45 MHz-IX GHz),” in IEEE Bipolar Circuits und Technology Meeting, Sep. 1987, pp.70-73. M. C. A. M. Koolen et al., “An improved de-embedding technique for on-wafer high-frequency characterization,” in IEEE Bipolar Circuits and Technology hdeeling, Sep. 1991, pp.188-191. C. H. Chen et al. “A general noise and S-parameter deembedding procedure for on-wafer high-frequency noise measuremenb of MOSFETs,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 1004-1005, May 2001. M. H. Cho et al., “A novel cascade-based de-embedding method for on-wafer microwave characterization and automatic measurement,” in IEEE MTT-S Int. Microwave Symp. Dig., pp. 1237-1240, Jun. 2004. M. H. Cho et al., “A novel cascade-based de-embedding method for on-wafer microwave characterization and automatic measurement,” in IEEE Radio Frequency integrated Circuits (RFIC) Symposium, pp.303 -306, June 2005. K. C. Gupta , Rakesh Chadha , Computer-Aided Design of Microwave Circuits, Artech House, Dec., 1981. R.-C. Liu, K.-L. Deng, and H. Wang, “A 0.6-22-GHz broad-band CMOS distributed amplifier,” in Dig. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2003, pp. 103-106. R.-C. Liu , C.-S. Lin , K.-L. Deng and H. Wang “A 0.5-14 GHz 10.6-dB CMOS cascade distributed amplifier,” IEEE VLSI Circuits Symp. Dig., pp. 139-140, 2003. K. W. Kobayashi, R. Esfandiari, and A. K. Oki, “A novel HBT distributed amplifier design topology based on attenuation compensation techniques,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2583-2589, Dec. 1994. A. Bevilacqua and A. M. Niknejad, “An ultra-wide-band CMOS low noise amplifier for 3.1 to 10.6-GHz wireless receiver,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259-2268, Dec. 2004. A. Ismail, A. Abidi, “A 3 to 10GHz LNA Using a Wideband LC-ladder Matching Network,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2269-2277, Dec. 2004. C.-W. Kim, M.-S. Kang, P. T. Anh, H.-T. Kim, and S.-G. Lee, “An ultra-wide-band CMOS low-noise amplifier for 3-5-GHz UWB system,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 544-547, Feb. 2005. R. Gharpurey, “A broadband low-noise front-end amplifier for ultra wideband in 0.13||摘要:||
本論文分為兩部份，第一部份為CMOS 90nm上應用於毫米波頻段之低損耗傳輸線研究。雙層嵌入式金屬層能夠減少傳輸線的損耗，但截止頻率並未受到影響。實驗中我們使用三種不同傳輸線架構，探討傳輸線的損耗行為。實驗結果為傳統傳輸線與嵌入式金屬層於第一層與第二層傳輸線相比較後，雙層嵌入式金屬層傳輸線有較低的損耗並未減少截止頻率。嵌入式金屬層傳輸線的損耗為268 dB/cm，傳統傳輸線的損耗為710 dB/cm。對於傳輸線的損耗，雙層嵌入式金屬層傳輸線有極大的改善適用於毫米波頻段上。最後，我們利用電性模型代入傳輸線的分析結果，模擬結果與實測資料相差無幾。
This thesis includes two topics. The first topic studies on low loss CPW transmission line for millimeter wave application in 90 nm CMOS technology. The twice cross-tie metal patterns is proposed to decrease transmission line loss and maintain operation bandwidth using nano-meter CMOS technology. Three transmission lines are implemented in this experiment. The measurement results show that the location of cross-tie metal patterns in metal-1 and metal-2 films exhibits the low attenuation constant and maintains the operation bandwidth compared with conventional transmission line. Moreover, the modeling effort is paid to analyze the experiment result. The result shows the attenuation constants with the values of 268 dB/cm and 710dB/cm for proposed and traditional Coplanar Waveguide (CPW) lines. A huge improvement is achieved to apply the transmission line in millimeter-wave operation using CMOS technology.
The second topic demonstrates the broadband CMOS amplifiers. A novel architecture is proposed to design broadband CMOS amplifiers in this thesis. The proposed architecture includes the two-stage cascade and shunt peaking techniques. Accordingly, the bandwidth-compensation is executed to achieve gain flatness, broadband, low noise, and low power performances. The low noise amplifier (LNA) was fabricated in TSMC 0.18-μm CMOS process. Measurement results show that the design circuit accomplishes the highest gain-bandwidth product, which has the value of 173 GHz, compared with reported works using a 0.18-μm CMOS technology. Moreover, an ultra-wide-band (UWB) low noise amplifier utilizing inductive feedback technique is proposed. The proposed UWB LNA was fabricated in CMOS 0.13-μm process. The implemented LNA presents a maximum power gain of 10 dB, and a good input matching of 50Ω over frequency band. An excellent noise figure (NF) of <5dB was obtained in the frequency range of 0.1-12 GHz, the amplifier with a power dissipation of 30 mW under a 2.5-V power supply.
|Appears in Collections:||電機工程學系所|
Show full item record
TAIR Related Article
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.