Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7941
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dc.contributor貢中元zh_TW
dc.contributorChung-Yuan Kungen_US
dc.contributor劉堂傑zh_TW
dc.contributorDon-Gey Liuen_US
dc.contributor.advisor劉漢文zh_TW
dc.contributor.advisorHan-Wen Liuen_US
dc.contributor.author林傑嵩zh_TW
dc.contributor.authorLin, Jie-Sungen_US
dc.contributor.other中興大學zh_TW
dc.date2009zh_TW
dc.date.accessioned2014-06-06T06:40:46Z-
dc.date.available2014-06-06T06:40:46Z-
dc.identifierU0005-1108200821213400zh_TW
dc.identifier.citation〔1〕 H. Kuriyama et al., “An asymmetric memory cell using a C-TFT for ULSI SRAM, ”Symp. On VLSI Tech., pp.38, 1992. 〔2〕 Yamauchi, N.; Inaba, Y.; Okamura, M, “An integrated Photodetector-amplifier using a-Si p-i-n photodiodes and poly-Sithin-film transistors, ”IEEE Photonics Technology Letters, Volume 5, Issue 3, pp. 319-321, 1993. 〔3〕 T. Yamanaka, T.Hashimoto, N.Hasegawa, T. Tanala, N. Hashimoto, A Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. 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Katoh, “Submicron-scale characterization of poly-Si thin films crystallized by excimer laser and continuous-wave laser, ” Journal of applied physics, Volume 95, Number 12, 2004 〔7〕 Yukiharu URAOKA, Koji KITAJIMA, Hiroshi KIRIMURA, Hiroshi YANO, Tomoaki HATAYAMA and Takashi FUYUKI, “Degradation in Low-Temperature Poly-Si Thin Film Transistors Depending on Grain Boundaries, ”Japanese Journal of Applied Physics Volume.44, No.5A, pp. 2895-2901, 2005. 〔8〕 Satoshi INOUE, Mutsumi KIMURA and Tatsuya SHIMODA“Analysis and Classification of Degradation Phenomena in Polycrystalline-Silicon Thin Film Transistors Fabricated by a Low-Temperature Process Using Emission Light Microscopy, ”Japanese Journal of Applied Physics. Volume.42, pp.1168-1173, 2003 〔9〕 Yoshiaki Toyota, Mieko Matsumura, Mutsuko Hatano, Takeo Shiba, Senior Member, IEEE, and Makoto Ohkura, Member,IEEE, “A New Study on the Degradation Mechanism in Low-Temperature P-Channel Polycrystalline Silicon TFTs Under Dynamic Stress,”IEEE transaction on electron device, VOL.53, NO.9, September, 2006. 〔10〕 Kook Chul Moon, Jas-Hoon Lee, and Min-Koo Han,“The Study of Hot-Carrier Stress on Poly-Si TFT Employing C-V measurement, ”IEEE transaction on electron device, Volume.52, NO.4, April, 2005 〔11〕 Yoshiaki Toyota, Takeo Shiba, Senior Member,IEEE, and Makoto Ohkura, Member, IEEE, “Effects of the Timing of AC Stress on Device Degradation Produced by Trap States in Low-Temperature Polycrystalline-Silicon TFTs, ” IEEE transaction on electron device, Volume.52, NO.8, August, 2005 〔12〕 Nikolaos A. Hastas, Charalabos A. Dimitriadis, Jean Brini, and George Kamarinos, “hot-carrier-induced degradation in short p-channel nonhydrogenated polysilicon thin-film transistors, ” IEEE transactions on electron devices, Volume.49, No.9, 2002 〔13〕 Ya-Hsiang Tai, Shih-Che Huang,, Chien Wen Lin, and Hao Lin Chiu, “Degradation of the Capacitance-Voltage Behaviors of the Low-Temperature Polysilicon TFTs under DC stress, ”Journal of The Electronchemical Society, 154(7) H611-H618, 2007 〔14〕 Yukiharu Uraoka, Hiroshi YANO, Tomoaki HATAYAMA and Takashi FUYUKI, “Comprehensive Study on Reliability of Low-Temperature Poly-Si Thin-Film Transistors under Dynamic Complimentary Metal-Oxide Semiconductor Operations, ”Japanese Journal of Applied Physics. Volume.41, pp. 2414-2418, 2002 〔15〕 Chin-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Sieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, and Tan-Fu Lei, “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors,”IEEE transactions on electron devices, Volume.53, No.12, December, 2006. 〔16〕 Shih-Che Huang, Yu-Han Kao, Ya-Hsiang Tai, “Study on electrical degradation of p-type low-temperature polycrystalline silicon thin film transistors with C-V measurement analysis,”Thin Solid Films 515 1206-1209, 2006. 〔17〕 Satoshi INOUE, Hiroyuki OHSIMA and Tatsuya SHIMODA,“Analysis of Degradation Phenomenon Caused by Self-Heating in Low-Temperature-Processed Polycrystalline Silicon Thin Film Transistors,” The Japan Society of Applied Physics, Volume.41, pp.6313-6319, 2002. 〔18〕 Kow Ming CHANG, Yuan Hung CHUNG and Gin Ming LIN,“Hot Carrier Induced Degradation in the Low Temperature Processed Polycrystalline Silicon Thin Film Transistors Using The dynamic Stress,” The Japan Society of Applied Physics, Volume.41, pp.1941-1946, 2002. 〔19〕 Yukiharu URAOKA, Hiroshi YANO, Tomoaki HATAYAMA and Takashi FUYUKI,“Comprehensive Study on Reliability of Low-Temperature Poly-Si Thin-Film Transistors under Dynamic Complimentary Metal-Oxide Semiconductor Operations,”The Japan Society of Applied Physics, Volume.41, pp.2414-2418, 2002. 〔20〕 Shen De WANG, Tzu Yun CHANG, Wei Hsiang Lo, Jen Yi SANG and Tan Fu LEI,“Drain/Gate-Voltage-Dependent On-Current and Off-Current Instabilities in Polycrystalline Silicon Thin-Film Transistors under Electrical Stress,”Japanese Journal of Applied Physics, Volume.44, No.9A, PP.6435-6440, 2005.zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/7941-
dc.description.abstract低溫複晶矽薄膜電晶體目前被廣泛的應用,甚至也達到與電路系統化的目標,不過,仍是有許多可靠度的問題存在。就工作於平面顯示器上時,元件本身則是在交流訊號下操作,此時就會有同步及非同步的問題產生。因此,測試低溫複晶矽薄膜電晶體在交流訊號下的可靠度是有其必然性的。在本篇論文中,我們探討低溫複晶矽薄膜電晶體之電性不穩定性,除了直流定電壓應力之電性不穩定性測試以外,我們再加入交流訊號應力之電性不穩定性測試。 (1) 直流定電壓下應力之電性不穩定性測試 我們將針對兩種主要造成低溫複晶矽薄膜電晶體退化的機制來作研究分析,分別是熱載子效應以及自發熱效應。對於N型低溫複晶矽薄膜電晶體我們發現分別在Vg=+3V、Vd=+15及Vg=+18V、Vd=+15V之直流定電壓應力條件下,在我們的元件上會發生較明顯熱載子效應及自發熱效應,而在P型低溫複晶矽薄膜電晶體方面,熱載子效應及自發熱效應則分別發生在Vg=-4V、Vd=-15V及Vg=-18V、Vd=-15V之直流定電壓應力條件下。在這部份的研究中,針對N型低溫複晶矽薄膜電晶體,我們發現了特別的現象,其發生的條件是在Vg=+18V、而加在汲極的電壓在小於+10V左右下,會有衰退反轉的情形。但是在高汲極電壓下,大約在+12V以上時,因載子撞擊汲極端而產生的缺陷主導了退化機制,所以反轉的現象就消失了。 (2) 交流訊號下應力之電性不穩定性測試 不管是在N型或是P型低溫複晶矽薄膜電晶體,在交流訊號下所作的應力測試,其衰退量是遠低於在直流定電壓下所作的。不過也僅侷限於通道在導通時的測試條件下。在此交流訊號下不穩定性之研究以N型低溫複晶矽薄膜電晶體為主。我們發現在高頻以及電壓範圍起始點使通道無法產生的應力條件下,亦即關閉區,其衰退情形是最嚴重的。而頻率與電壓範圍起始點也有極大的關聯性。最後,在電壓切換時間的探討裡,使元件產生退化的原因推斷是在產生電洞及釋放電洞時,而非由通道形成後進入關閉時所釋放的電子撞擊產生退化。zh_TW
dc.description.abstractLTPS (Low Temperature Poly-Si) TFTs have been widely used recently, moreover it also achieves the target of combining the circuit system on the panel, but they still have the electrical instability issue on some applications. When the LTPS TFTs work on the flat panel display, the TFTs are operated under the AC signal. At the same time, the problems of synchronous and asynchronous signals would be exit. Thus, it is necessary to study the instability of the LTPS TFTs under the AC signal stress. In this thesis, we will discuss the electrical instability of LTPS TFTs. Beside the instability of DC bias stress, we even study the instability of the AC signal stress. (1) The electrical instability of the DC stress Under the DC bias stress, we focus on the two dominant mechanisms that cause the LTPS TFTs degradation, and the two mechanisms are hot-carrier and self-heating effects. For the N-type LTPS TFTs, we find that the hot-carrier and self-heating effects are happened under Vg=+3V、Vd=+15 and Vg=+18V、Vd=+15V, respectively. For the P-type LTPS TFTs, the hot-carrier and self-heating effect are happened under Vg=-4V、Vd=-15 and Vg=-18V、Vd=-15V, respectively. On this researching topic, for the N-type LTPS TFTs, we find a special phenomenon. When the Vg=+18V and drain bias voltage is smaller than +10V, there is a turn-around phenomenon in the degradation trend. But under the high drain bias voltage, about more than +12V, the turn-around phenomenon would disappear owing to the defects which are generated by the carrier impacting the drain terminal, and they dominate the mechanism of the degradation. (2) The electrical instability of the AC stress Despite in the N-type and P-type LTPS TFTs, the degradation under AC stress is less than that under DC stress localized under the conditions resulting the channel into the on region. To study the instability of AC stress simply, we focus on the N-type LTPS TFTs. We find that the degradation is much more serious in the high frequency and the initial point of the same stress voltage range resulting in no channel generation i.e. off region. And the stress frequency has a strong relationship on the initial point of the stress voltage range. Finally, in the study of the transfering voltage, we find the cause of the TFTs degradation is the time of the holes generated and released, not the time of the released electron impact from the on region into the off region.zh_TW
dc.description.tableofcontents致謝 i 中文摘要 ii Abstract iii 目次 iv 表目次 vii 圖目次 viii 第一章 簡介 1 1.1低溫複晶矽薄膜電晶體 1 1.2 可靠度工程 3 1.3 文獻探討 6 1.4 研究動機 8 第二章 元件介紹及基本原理 9 2.1 元件製作流程 9 2.2 量測系統設定及電性參數定義 11 2.2.1量測系統介紹 11 2.2.2 交流訊號波形圖 13 2.2.3 電性參數的粹取 14 第三章 量測方法及流程 17 3.1 直流定電壓下之電性不穩定性測試 17 3.2 交流訊號下電性不穩定性測試 18 第四章 結果與討論 21 4.1 直流定電壓應力下之電性不穩定性測試 21 4.1.1 熱載子效應之應力測試 (N-type) 21 4.1.2 熱載子效應之應力測試 (P-type) 21 4.1.3 自發熱效應之應力測試 (N-type) 35 4.1.4 自發熱效應之應力測試 (P-type) 35 4.1.5 衰退反轉現象(N-type) 49 4.2 交流訊號應力下之電性不穩定性測試 56 4.2.1 固定交流訊號電壓於閘極之應力測試(N-type) 56 4.2.2 固定交流訊號電壓於閘極之應力測試(P-type) 56 4.2.3 頻率10kHz及改變電壓範圍起始點於閘極之可靠度測試 68 4.2.4 頻率1MHz及改變電壓範圍起始點於閘極之可靠度測試 78 4.2.5 在各種頻率下改變交流訊號電壓範圍起始點於閘極之比較 82 4.2.6 改變交流訊號電壓範圍起始點及切換時間於閘極之可靠度測試 95 第五章 結論 112 參考文獻 114zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1108200821213400en_US
dc.subjectLTPSen_US
dc.subject低溫複晶矽薄膜電體zh_TW
dc.subjectThe electrical instability of the DC stressen_US
dc.subjectreliabilityen_US
dc.subjecthot-carrieren_US
dc.subjectself-heatingen_US
dc.subjectThe electrical instability of the DC stressen_US
dc.subject直流定電壓應力測試zh_TW
dc.subject可靠度zh_TW
dc.subject熱載子zh_TW
dc.subject自發熱zh_TW
dc.subject交流訊號應力測試zh_TW
dc.title低溫複晶矽薄膜電晶體在直流與交流電壓應力下不穩定性之研究zh_TW
dc.titleStudy on the Instability of Low Temperature Poly-Si Thin Film Transistors under DC and AC Stressen_US
dc.typeThesis and Dissertationzh_TW
item.languageiso639-1en_US-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
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