Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8045
標題: 使用QR分解和交錯近似法 於奇異值分解之硬體實現
SVD Hardware Implementation Using QRD and Interleaver Approximation Method
作者: 陳志勝
Chen, Chih-Sheng
關鍵字: SVD;奇異值分解;QRD;Interleaver;eigenvalue and eigenvector;QR分解;交錯近似法;特徵值;特徵向量
出版社: 電機工程學系所
引用: [1] H. Heiskala and J.T. Terry , OFDM Wireless LANs: A Theoretical and Practical Guide,Sams Psublishing,2002. [2] J.K.Zhang and A.Kavcic,“Equal-diagonal QR decomposition and its application to precoder design for successive-cancellation detection,”IEEE Transactions Information Theory, vol.51,no.1 pp.154-172,Jan. 2005. [3] K.-H.Lin,R.C.Chang, and C.-F. Wu,“Hardward architecture of improved Tomlinson-Harashima precoding for downlink MC-CDMA,”IEEE Asia Pacific Conference on Circuit and Systems , Singapore , Dec. 2006. [4] V. Strumpen, H. Hoffmann, A. Agrwal ,” A stream algorithm for the SVD ” ,Technical Memo MIT-LCS-TM-641 ,October 22,2003. [5] J.R. Cavallaro, M.P. Keleher, R.H. Price and G.S. Thomas , ”VLSI Implementation of a CORDIC Processor”,Industry Microelectronics Symposium,pp.256-260,June 1989. [6] G.Hori, ”A general framework for SVD flows and joint SVD flows”, IEEE International Conference on Acoustics, Speech, and Signal Processing,vol.2,pp.II-693, April 2003. [7] M.Jun, K.K.Parhi, E.F.Deprettere, “A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms,” IEEE Transactions Signal Processing, vol. 49,no.2,pp.424-437,Feb.2001. [8] N.D. Hemyumar, J.R. Cavallaro, “A systolic VLSI architecture for complex SVD,”IEEE International Symposium on Circuits and Systems, vol.3,pp.1061-1064,May 1992. [9] M.A. Hassan and A.A. Hasan, “Fast approximated sub-space algorithms”, IEEE Workshop on Statistical Signal and Array Processing, pp.127-130,Aug.2000. [10] M. Weiwei, M.E. Kaye, D.M. Luke, and R. Doraiswami, ”An FPGA-Base Singular Value Decomposition Processor”, Canadian Conference on Electrical and Computer Engineering, pp.1047-1050,May 2006. [11] C. Studer, P. Lucthi, and W. Fiehtncr, “VLSI architecture for data-reduced steering matrix feedback in MIMO Systems”, IEEE International Symposium on Circuits and Systems,pp.300-303, May 2008. [12] H.A. Abdallah, Y.H. Hu “Parallel VLSI computing array implementation for signal subspace updating algorithm", IEEE International Conference on Acoustics, speech, and Signal Processing, vol.12, no.5, pp.779-782, Apr 1987. [13] P. Feldmann “Model order reduction techniques for linear system with large numbers of terminals” , Design, Automation and Test in Europe Conference and Exhibition, vol.2, pp.944-947, Feb.2004. [14] H.T. Chi and S. Weiss, ”Design of Precoding and Equalization for Broadband MIMO Transmission”, Conference Record on Signals, Systems and Computers, pp.1616-1620, Nov. 2007. [15] K.K.Parhi, “Algorithm transformation techniques for concurrent processors” ,IEEE PROCEEDINGS ,vol.77,no.12, pp.1879-1895,Dec. 1989.
摘要: 
奇異值分解( SVD )已成為標準線性代數的工具,在數位訊號處理上
基於CORDIC設計基於SVD的算法是其中最受歡迎的,其基本概念就是把每
一個矩陣,都化簡成對角矩陣。這樣在Beamforming的應用上,將會非常的方便,也就是降低困難度。大部分的奇異值分解演算法,都是以大量的運算式來求出奇異值的解,例如矩陣的特徵值與特徵向量就是以不斷的乘法之化簡最後達到結果。本篇論文,是以QR為基礎,配合交錯式近似法,來求得奇異值的解,QR分解是以Given Rotation 為基礎,這種方式是建構在CORDIC演算法上,只利用很簡單的加法以及位移達到分解目的,而交錯式近似法 ,則完全使用位移暫存的方式,故用這兩種方式的配合,可達得到低複雜度的奇異值分解之目的。

本篇論文電路實現是採用聯電0.18um 1P6M CMOS製程。實體面積為1000x930 ,執行速度為7MHz

SVD is a standard tool of linear algebra. SVD in digital signal processing based on the CORDIC is the most popular algorithm now. The fundamental concept of SVD is to simplify every matrix to be a diagonal matrix. On the application of beamforming, this method will be very convenient for calculation. Most SVD algorithm used a lot of calculation to find out the solution. For example, matrix's eigenvalues and eigenvectors are obtained by using multiplication continuously.
At last, we can get the most simplified result. In this thesis, QR base and
Interleaver approximation method is used to obtain the solution of SVD. Given Rotation is utilized for QR. Furthermore, Given Rotation method is established on CORDIC algorithm. Not only CORDIC algorithm uses very simple additions and shift registers to achieve the goal, but also Staggered Approximation uses shift registers toaccomplish.
As the result, the SVD hardware by using QR and Interleaver approximation method is very simple and small in area. The SVD circuit is designed by using UMC 0.18um 1P6M CMOS technology. The chip area is 1000x930 at 7MHz execution speed.
URI: http://hdl.handle.net/11455/8045
其他識別: U0005-1408200816491300
Appears in Collections:電機工程學系所

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