Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8114
標題: 三角積分脈波寬度調變之可程式化時脈寬度產生器
A Programmable Duty Cycle Generator Based on a Delta-Sigma PWM Mechanism
作者: 林冠宇
Lin, Gung-Yu
關鍵字: pulse width modulation;脈波寬度調變;clock generator;時脈產生器
出版社: 電機工程學系所
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摘要: 
近年來,大多數的數位與混合訊號電路中會大量的使用時脈訊號(clock)來控制電路,然而在高頻操作下,時脈訊號的頻率(frequency)、相位(phase)以及脈波寬度比例(duty-cycle)等特性之精準度十分重要。因此針對相位與頻率的校正上已發展出鎖相迴路(PLL)與延遲鎖定迴路(DLL)等相當成熟的技術,首先我們針對近年來應用於脈波寬度控制迴路的電路設計進行分析探討,並分析各種方法的優點與所面臨的挑戰,本論文著重於有可變的工作週期脈波寬度(duty-cycle)的控制部份,我們將提出不同於傳統的PWCL一個嶄新的架構,為可程式化時脈週期產生器,除了能提供50% duty cycle的校正之外,並發展其他duty-cycle的時脈輸出訊號,此電路利用二階的三角積分器來產生更多的工作週期,能由外部的數位訊號控制到7bits的解析度,因此此電路擁有更多的duty-cycle時脈輸出的選擇。本論文模擬設計於TSMC公司下線製造,我們用0.18μm CMOS 製程參數設計且操作電壓為1.8V 時,整合電路可操作在500MHz~800MHz 之間。電路中將脈波寬度及相位皆完成鎖定。經過SPICE 模擬,迴路在600MHz 的頻率下,可校正輸入訊號為10%~90%,將相位及脈波寬度皆鎖定後,輸出時脈訊號可在25%~75% 的duty-cycle之間做調整,且每次調整為0.78%,消耗的功率約為60mW,脈波寬度抖動(pulse-width jitter)約為8.6ps。

Recently, Most digital and mixed-signal circuits use a lot of clock signals to control a periodic notification at the requested time. The accuracies on frequencies, phases and pulse widths duty-cycle of clock signals are very important for high speed applications. It had mature advanced a phase locked loop (PLL) and a delay locked loop (DLL) technologies have achieved good results in recent years. First, we analysis and treat in connection with the pulse-width control loop(PWCL) applications and architectonics recently, and analysis the advantage of different ways and which challenge we to face. The thesis will emphasize the control of the variable duty-cycle. Different from the conventional DCC and PWCL, A new programmable duty-cycle generator (PDCG) with variable duty cycle of output clock and synchronization of the input clock and output clock is proposed. Since the conventional pulse-width control circuits can adjust duty cycle but can’t synchronize the input and output clocks, the proposed PDCG uses a 2nd-order Δ-Σ modulator to produce more several kinds of duty-cycle selection of clock signals with a 7-bit resolution. Simulated in a 0.18um CMOS technology, the proposed PDCG can operate from 500MHz to 800MHz and the duty-cycle range of input clock can be operated from 10% to 90%. Moreover, the duty cycle of the output clock can be adjusted from 25% to 75% in a fine step of 0.78%. The power dissipation is 60 mW. The pulse-width jitter is 8.6ps。
URI: http://hdl.handle.net/11455/8114
其他識別: U0005-1808200815483400
Appears in Collections:電機工程學系所

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