Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8132
標題: 多值邏輯快閃式記憶晶胞之研究
Investigation of Multi-Level Flash Memory Cells
作者: 葉志凌
Yeh, Chih Ling
關鍵字: Flash Memory;快閃記憶體;Dual Floating Gate;Silicon on Insulator;雙浮動閘;絕緣體上矽
出版社: 電機工程學系
摘要: 
多值邏輯準位快閃記憶體技術對於高記憶體密度的要求是可以實現又具備低價格的方法。以往多邏輯準位快閃記憶體技術,利用單浮動閘快閃記憶體給不同的閘極偏壓或不同的源極與汲極脈衝長度,來控制儲存在浮動閘中的電荷量,達成多邏輯準位的實現,缺點是為了達到電荷量能精確寫入浮動閘,週邊電路會變得更加複雜。因此,我們使用雙浮動閘快閃記憶體與其合適的操作方式來達到多值邏輯儲存的功能。在寫入操作時,採取熱電子與F-N穿遂兩種方式,在熱電子寫入時,因元件具有不同的源極/汲極的掺雜濃度與掺雜能量,產生明確的四個邏輯準位而不需變換不同的閘極電壓。使用F-N穿遂寫入時,我們提出不同的寫入電壓與不同的寫入時間二種改善方式,達到較明顯的邏輯準位差距。本篇的論文是依照模擬上的製程條件,透過國家奈米實驗室(NDL)來完成實際的雙浮動閘快閃記憶體的製作,並對元件做寫入與讀取的量測探討。另外,由於可攜式的資訊產品市場對於快閃記憶體除了對高密度的要求之外,更要求其能達到低功率與高效能,使用絕緣上矽(SOI)的技術,是可以改善效能並且減少功率消耗,為了未來快閃記憶體可以整合SOI技術,所以我們也研究SOI雙浮動閘快閃記憶體作寫入與讀取。

The technology of multilevel Flash E2PROM cells is capable of increasing the density of bits per unit area and decreasing the cost of products. In the prior arts, to control the charge stored in the floating gate for multilevel operation, variable voltages or pulses are applied to the control gate or the drain/source junctions. The peripheral circuits become more complicated. We proposed the dual floating gate (DFG) Flash cell and operation scheme to accomplish multilevel operation. The cell is programming by Channel hot electrons (CHE) and Fowler-Nordheim (FN) tunneling, while erased by channel Fowler-Nordheim tunneling to remove the charge in the floating gates. Due to the different source and drain doping concentrations and doping energies, it is not required to generate different voltages to achieve four-level operation. Use the FN tunneling programming, We proposed two modification methods, including variable writing voltages and programming times for multilevel operation. In this thesis, we report measurement of the dual floating gate flash cells fabricated by NDL to verify the operation including program/read schemes. Besides, the portable computing market requires high density, low power, high performance, which make SOI technology to be a good candidate. Therefore, flash memories integrated in SOI technology may be a good trend. Here, the programming and reading for SOI dual floating gate flash memory was also investigated.
URI: http://hdl.handle.net/11455/8132
Appears in Collections:電機工程學系所

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