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標題: 使用雙延遲鎖相迴路自我校正的游標尺式時間至數位轉換器
A Vernier-Based Time-to-Digital Converter with Dual DLLs for Self-Calibration
作者: 陳世璋
Chen, Shih-Chung
關鍵字: Delay Lock Loop;延遲鎖相迴路;Time-to-Digital Converter;時間至數位轉換器
出版社: 電機工程學系所
引用: 【1】Jorgen Christiansen, “Design and Characterization of CMOS High-Resolution Time-to-Digital Converters,” Ph.D. Dissertation,Universidade Tecnica De Lisboa Instituto Superior Tecnico, October 2000. 【2】楊澤龍, “應用於微刺激系統之電流自我校正八位元逐漸趨近式類比數位轉換器,” 國立中正大學電機工程研究所碩士論文, 2005 【3】李谷桓, “兩級游標尺延遲線之時間數位轉換器,” 國立清華大學工程與系統科學研究所碩士論文, 2004 【4】 B. K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle,E. Breeding and K. M. Baldwin, “A 100-ps Time-Resolution CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications,” IEEE J. Solid-State Circuits, vol.39, no.11, pp. 1839 - 1852, Nov. 2004 【5】Poki Chen, Chun-Chi Chen and You-Sheng Shen, “A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching,”IEEE Transactions on Nuclear Science, vol.53, no.4, pp.2215-2220, Aug. 2006 【6】Jorgen Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops, IEEE J. Solid-State Circuits, vol.31, no.7, pp. 952-957, July 1996 【7】Elvi Raisanen-Ruosalainen, etc. “A Low-Power CMOS Time-to-Digital Converter,” IEEE J. Solid-State Circuits, vol.30, no.9, pp. 984-990, Sept. 1995 【8】Poki Chen and Shen-Iuan Liu , “A Cyclic CMOS Time-to-DigitalConverter With Deep Sub-nanosecond Resolution, Proceedings of theIEEE 1999 Custom Integrated Circuits, pp. 605-608, May 1999 【9】J. P. Jansson, A. Man1tyniemi, and J. Kostamovaara, “A CMOS Time-to-Digital Converter With Better Than 10ps Single-Shot Precision,”IEEE J. Solid-State Circuits, vol.41, no.6, pp.1286-1296, June 2006 【10】M. S. Gorbics, J. Kelly, K. M. Roberts, R. L. Sumner, “A High Resolution Multihit Time to Digital Converter Integrated Circuit,” IEEE Conference Record. Nuclear Science Symposium, vol.1, pp. 421- 425,Nov. 1996 【11】P.Dudek, S. Szczepanski and J. V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-State Circuits, vol.35, no.2, pp.240-247, Feb. 2000 【12】 A. H. Chan and G. W. Roberts, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.1, pp. 79-95, Jan. 2004 【13】 Poki Chen, Chun-Chi Chen, Jia-Chi Zheng and You-Sheng Shen, “A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy,” IEEE Transactions on Nuclear Science, vol.54, no.2, pp.294-302, April 2007 【14】 劉深淵、楊清淵, 鎖相迴路,滄海書局, 2006 【15】 Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE J. Solid-State Circuits, vol.37, no.8, pp.1021-1027, Aug. 2002 【16】黃崇禧,“互補式金半延遲鎖定迴路在時脈合成器與時間至數位轉換器之設計與應用,”國立臺灣大學電機工程學研究所博士論文, 2004 【17】Joonsuk Lee and Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop With Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits, vol.35, no.8, pp. 1137-1145, Aug. 2000 【18】R. Hossain, L. D. Wronski and A. Albicki, “Low Power Design Using Double Edge Triggered Flip-Flops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.2, no.2, pp. 261-265, June 1994 【19】Neil H. E. Weste and David Harris, CMOS VLSI Design-A Circuits and Systems Perspective, Third Edition, Addison Wesley, 2004 【20】M. Afghahi, “A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applications,” IEEE J. Solid-State Circuits, vol.31, no.2, pp. 247-254, Feb. 1996 【21】 李瑜,“應用於晶片間通訊的時脈資料回復電路及高效率介面電路之設計,” 國立中興大學電機工程研究所碩士論文, 2005 【22】 張耿豪, “使用振盪時脈相位對正技術之時脈與資料回復電路設計,”國立中興大學電機工程研究所碩士論文, 2006 【23】 M. Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers,” IEEE J. Solid-State Circuits, vol.26, no.2, pp. 165-168, Feb. 1991 【24】 Shao-Ku Kao, Bo-Jiun Chen and Shen-Iuan Liu, “ A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop,” IEEE Transactions on Circuits and Systems-II:Express Briefs, vol. 54, no.7, pp. 566-570, July 2007 【25】 Chorng-Sii Hwang, Poki Chen, and Hen-Wai Taso, “A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,”IEEE Transactions on Nuclear Science, vol. 51, NO. 4, August 2004
此電路是以台積電0.18um 1P6M的製程實現。產生的解析度為19.25ps
,輸入範圍為2.56μs。模擬得到的短範圍微分非線性誤差為0~0.91LSB,積分非線性誤差為0~0.91LSB,長範圍微分非線性誤差為-0.02~0.02LSB,積分非線性誤差為0~0.02LSB。功率消耗為140mW,晶片面積為1370×1220 μm2。

Time-to-digital converters (TDC) are widely used in various situations. Such as time-of-flight (T.O.F.) particle detectors, laser range finders, oscilloscopes, logic analyzers and some other industrial applications. How to produce a wide Input Range and high resolution TDC is an important issue in this paper. On the other hand, only if the resolution is insensitive to environment variations, will the measurement results be reliable. A TDC with calibration circuit can reduce the measurement errors caused by operation temperature, process parameter, and operation voltage effectively.
We present a new type Vernier-based TDC that can increase the Input Range and remain the feature of high resolution in this paper. We use a dual delay-locked loops (DLL) to provide about 20ps delay based on a single reference clock. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration circuit problems.
The circuit is fabricated in the TSMC 0.18um 1P6M technology. The simulated short range differential nonlinearity is 0 ~ 0.91 LSB, and the simulated short range integral nonlinearity is 0 ~ 0.91 LSB. The long range differential nonlinearity is -0.02 ~ 0.02 LSB, and the long range integral nonlinearity is 0 ~ 0.91 LSB. The power consumption is 140mW and the chip size is 13701220 um2.
其他識別: U0005-1908200814053200
Appears in Collections:電機工程學系所

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