Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8153
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dc.contributor盧志文zh_TW
dc.contributorChih-Wen Luen_US
dc.contributor張順志zh_TW
dc.contributorSoon-Jyh Changen_US
dc.contributor.advisor楊清淵zh_TW
dc.contributor.advisorChing-Yuan Yangen_US
dc.contributor.author陳世璋zh_TW
dc.contributor.authorChen, Shih-Chungen_US
dc.contributor.other中興大學zh_TW
dc.date2009zh_TW
dc.date.accessioned2014-06-06T06:41:05Z-
dc.date.available2014-06-06T06:41:05Z-
dc.identifierU0005-1908200814053200zh_TW
dc.identifier.citation【1】Jorgen Christiansen, “Design and Characterization of CMOS High-Resolution Time-to-Digital Converters,” Ph.D. Dissertation,Universidade Tecnica De Lisboa Instituto Superior Tecnico, October 2000. 【2】楊澤龍, “應用於微刺激系統之電流自我校正八位元逐漸趨近式類比數位轉換器,” 國立中正大學電機工程研究所碩士論文, 2005 【3】李谷桓, “兩級游標尺延遲線之時間數位轉換器,” 國立清華大學工程與系統科學研究所碩士論文, 2004 【4】 B. K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle,E. Breeding and K. M. Baldwin, “A 100-ps Time-Resolution CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications,” IEEE J. Solid-State Circuits, vol.39, no.11, pp. 1839 - 1852, Nov. 2004 【5】Poki Chen, Chun-Chi Chen and You-Sheng Shen, “A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching,”IEEE Transactions on Nuclear Science, vol.53, no.4, pp.2215-2220, Aug. 2006 【6】Jorgen Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops, IEEE J. Solid-State Circuits, vol.31, no.7, pp. 952-957, July 1996 【7】Elvi Raisanen-Ruosalainen, etc. “A Low-Power CMOS Time-to-Digital Converter,” IEEE J. Solid-State Circuits, vol.30, no.9, pp. 984-990, Sept. 1995 【8】Poki Chen and Shen-Iuan Liu , “A Cyclic CMOS Time-to-DigitalConverter With Deep Sub-nanosecond Resolution, Proceedings of theIEEE 1999 Custom Integrated Circuits, pp. 605-608, May 1999 【9】J. P. Jansson, A. Man1tyniemi, and J. Kostamovaara, “A CMOS Time-to-Digital Converter With Better Than 10ps Single-Shot Precision,”IEEE J. Solid-State Circuits, vol.41, no.6, pp.1286-1296, June 2006 【10】M. S. Gorbics, J. Kelly, K. M. Roberts, R. L. Sumner, “A High Resolution Multihit Time to Digital Converter Integrated Circuit,” IEEE Conference Record. Nuclear Science Symposium, vol.1, pp. 421- 425,Nov. 1996 【11】P.Dudek, S. Szczepanski and J. V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-State Circuits, vol.35, no.2, pp.240-247, Feb. 2000 【12】 A. H. Chan and G. W. Roberts, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.1, pp. 79-95, Jan. 2004 【13】 Poki Chen, Chun-Chi Chen, Jia-Chi Zheng and You-Sheng Shen, “A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy,” IEEE Transactions on Nuclear Science, vol.54, no.2, pp.294-302, April 2007 【14】 劉深淵、楊清淵, 鎖相迴路,滄海書局, 2006 【15】 Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE J. Solid-State Circuits, vol.37, no.8, pp.1021-1027, Aug. 2002 【16】黃崇禧,“互補式金半延遲鎖定迴路在時脈合成器與時間至數位轉換器之設計與應用,”國立臺灣大學電機工程學研究所博士論文, 2004 【17】Joonsuk Lee and Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop With Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits, vol.35, no.8, pp. 1137-1145, Aug. 2000 【18】R. Hossain, L. D. Wronski and A. Albicki, “Low Power Design Using Double Edge Triggered Flip-Flops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.2, no.2, pp. 261-265, June 1994 【19】Neil H. E. Weste and David Harris, CMOS VLSI Design-A Circuits and Systems Perspective, Third Edition, Addison Wesley, 2004 【20】M. Afghahi, “A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applications,” IEEE J. Solid-State Circuits, vol.31, no.2, pp. 247-254, Feb. 1996 【21】 李瑜,“應用於晶片間通訊的時脈資料回復電路及高效率介面電路之設計,” 國立中興大學電機工程研究所碩士論文, 2005 【22】 張耿豪, “使用振盪時脈相位對正技術之時脈與資料回復電路設計,”國立中興大學電機工程研究所碩士論文, 2006 【23】 M. Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers,” IEEE J. Solid-State Circuits, vol.26, no.2, pp. 165-168, Feb. 1991 【24】 Shao-Ku Kao, Bo-Jiun Chen and Shen-Iuan Liu, “ A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop,” IEEE Transactions on Circuits and Systems-II:Express Briefs, vol. 54, no.7, pp. 566-570, July 2007 【25】 Chorng-Sii Hwang, Poki Chen, and Hen-Wai Taso, “A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,”IEEE Transactions on Nuclear Science, vol. 51, NO. 4, August 2004zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/8153-
dc.description.abstract時間至數位轉換器被廣泛地應用於飛行時間粒子檢測器、雷射測距儀、示波器、邏輯分析儀以及其它工業應用中。如何產生一個寬輸入範圍、高解析度的時間至數位轉換器是本論文的重點。另一方面,解析度必須不易受外在環境的影響,得到的量測結果才具有參考性。一個擁有校正電路的時間至數位轉換器能有效降低因操作溫度、製程參數和操作電壓變動所產生的量測誤差。 在本論文中,我們展示出一個新型的游標尺式時間至數位轉換器,可以有效增加輸入範圍和保持高解析度的特色。我們使用一個單一參考時脈的雙迴路延遲鎖相迴路當成校正電路。所提出的時間至數位轉換器可以成功地消除元件間的誤差、輸入範圍的限制、外部偏壓的調整和複雜的校正電路等問題。 此電路是以台積電0.18um 1P6M的製程實現。產生的解析度為19.25ps ,輸入範圍為2.56μs。模擬得到的短範圍微分非線性誤差為0~0.91LSB,積分非線性誤差為0~0.91LSB,長範圍微分非線性誤差為-0.02~0.02LSB,積分非線性誤差為0~0.02LSB。功率消耗為140mW,晶片面積為1370×1220 μm2。zh_TW
dc.description.abstractTime-to-digital converters (TDC) are widely used in various situations. Such as time-of-flight (T.O.F.) particle detectors, laser range finders, oscilloscopes, logic analyzers and some other industrial applications. How to produce a wide Input Range and high resolution TDC is an important issue in this paper. On the other hand, only if the resolution is insensitive to environment variations, will the measurement results be reliable. A TDC with calibration circuit can reduce the measurement errors caused by operation temperature, process parameter, and operation voltage effectively. We present a new type Vernier-based TDC that can increase the Input Range and remain the feature of high resolution in this paper. We use a dual delay-locked loops (DLL) to provide about 20ps delay based on a single reference clock. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration circuit problems. The circuit is fabricated in the TSMC 0.18um 1P6M technology. The simulated short range differential nonlinearity is 0 ~ 0.91 LSB, and the simulated short range integral nonlinearity is 0 ~ 0.91 LSB. The long range differential nonlinearity is -0.02 ~ 0.02 LSB, and the long range integral nonlinearity is 0 ~ 0.91 LSB. The power consumption is 140mW and the chip size is 13701220 um2.en_US
dc.description.tableofcontents誌謝 -i- 摘要 -ii- Abstract -iii- 目錄 -iv- 圖目錄 -vi- 表目錄 -ix- 第一章 緒論 -1- 1-1 研究動機 -1- 1-2 論文架構 -2- 第二章 研究基礎 -3- 2-1 效能參數 -3- 2-1.1 輸入範圍(Input Range)、解析度(Resolution) -3- 2-1.2 位移誤差(Offset Error) -4- 2-1.3 增益誤差(Gain Error) -4- 2-1.4 微分非線性誤差(Differential Nonlinearity Error) -5- 2-1.5 積分非線性誤差(Integral Nonlinearity Error) -5- 2-1.6 柱狀圖(Histogram) -6- 2-2 架構比較 -7- 2-2.1 時間轉電壓式時間至數位轉換器 -7- 2-2.2 雙斜率式時間至數位轉換器 -8- 2-2.3 延遲鎖相迴路陣列式時間至數位轉換器 -9- 2-2.4 脈衝縮減延遲式時間至數位轉換器 -10- 2-2.5 多層級內插式時間至數位轉換器 -12- 2-2.6 游標尺式時間至數位轉換器 -14- 第三章 電路設計 -18- 3-1 架構由來 -18- 3-1.1 想法起源 -18- 3-1.2 比較差異 -18- 3-2 整體架構 -22- 3-2.1 系統架構圖 -22- 3-2.2 訊號處理時脈圖 -23- 3-2.3 規格設定 -25- 3-3 延遲鎖相迴路及游標尺延遲線 -26- 3-3.1 延遲鎖相迴路 -26- 3-3.2 游標尺延遲線 -38- 3-4 控制電路 -43- 3-4.1 互補傳輸閘邏輯及多工器 -44- 3-4.2 雙端真單相時脈D型正反器 -45- 3-5 解碼電路 -46- 3-5.1 解決(1,0)問題的電路 -46- 3-5.2 解碼電路 -47- 3-6 其他電路 -48- 3-6.1 線性電路 -48- 3-6.2 單端輸入轉雙端輸出電路 -49- 3-6.3 雙端輸入轉單端輸出電路 -50- 3-6.4 雙端輸入轉雙端輸出電路 -50- 3-6.5 非同步計數器 -51- 3-6.6 補助鎖定電路 -51- 3-6.7 量測考量電路 -52- 第四章 模擬結果及量測設置 -54- 4-1 模擬結果 -54- 4-1.1 雙延遲鎖相迴路系統 -54- 4-1.2 游標尺相關電路 -58- 4-1.3 整體時間至數位轉換器 -60- 4-2 量測設置 -62- 4-2.1 Data Sheet -62- 4-2.2 量測考量 -63- 第五章 結論 -65- 參考文獻 -66-zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1908200814053200en_US
dc.subjectDelay Lock Loopen_US
dc.subject延遲鎖相迴路zh_TW
dc.subjectTime-to-Digital Converteren_US
dc.subject時間至數位轉換器zh_TW
dc.title使用雙延遲鎖相迴路自我校正的游標尺式時間至數位轉換器zh_TW
dc.titleA Vernier-Based Time-to-Digital Converter with Dual DLLs for Self-Calibrationen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
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