Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8159
標題: 嵌入式多階判讀EEPROM電路與系統設計
Circuits and Systems Design for Multi-level Identifying Embedded EEPROM
作者: 賴彌元
Lai, Mi-Yuan
關鍵字: Multi-level Identifying;多階判讀;Embedded;EEPROM;嵌入式;記憶體
出版社: 電機工程學系所
引用: [1] 李昆鴻,”Study of High-Qensity Embedded Single-Polysilicon Nonvolatile Memory ,” 2005年博士論文,清華大學. [2] Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications,” VLSI Technology Symposium, Kyoto, Japan, pp. 93-94, 2003. [3] C. –S. E. Yang, et al., “New buried bit-line NAND (Bi-NAND) Flash memory for data storage,” Symp. VLSI Tech. Dig., pp. 95-96, 2003. [4] H.-F. A. Chou, et al., “Comprehensive study on a novel bi-directional tunneling program/erase NOR-type (Bi-NOR) 3-D flash memory cell,” IEEE Trans. Electron Devices, vol. 48, pp. 1386-1393, 2001. [5] A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas, and A. Arapoyanni, “A new Flash memory sense amplifier in 0.18 μm CMOS technology,” Proc. IEEE Int. Conf. Electronics, circuits, and Systems (ICECS), vol. 2, pp. 941-944, Sep., 2001. [6] J. F. Dickson, “On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. sc-11, pp. 374-378,Jun., 1976. [7] Hong-chin Lin and Nai-Hsien Chen, “An Efficient Clock Scheme for Low-voltage Four-phase Charge Pumps,” IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 504-507, 2001. [8] D. Hilbiber “A new Semiconductor voltage standard,” in ISSCC Dig. Tech. Papers, pp. 32-33, Feb. 1964. [9] K. E. Kujik. “A Precision Reference Voltage Source” IEEE J.Solid-State Circuits, vol. 8, pp. 222-226, Jun., 1973. [10] G. Campardo, R. Micheloni, D. Novosel, ”VLSI-Design of Non-Volatile Memories,” Springer,Oct., 2004. [11] K. Itoh, ”VLSI Memory chip Design,” Springer, Jan., 2001 [12] Chiu-Chiao Chung, Hong-chin Lin,Yen-Tai Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories,” IEEEJ. solid-state circuits, vol. 2,Feb., 2005. [13] Chiu-Chiao Chung, Hong-chin Lin,You-Min Shen and Yen-Tai Lin, “A Multilevel Sensing and Program verifying scheme for Bi-NAND Flash Memories,” IEEE VLSI-TSA International Symposium, pp. 267-270, apr., 2005. [14] Chiu-Chiao Chung, Hongchin Lin, and Yen-Tai Lin,”A Multilevel Read and Verifying Scheme for Bi-NAND Flash Memories,” IEEE J. solid-state circuits, vol. 42, MAY, 2007. [15] R. Micheloni, L. Crippa, M. Sangalli, and G. Campardo, “The Flash Memory Read Path: Build Blocks and Critical Aspects,”proceedings of IEEE, pp. 537-553, Apr., 2003. [16] 林映助,”Circuits and System Design for Embedded EEPROM ,” 2007年碩士論文,中興大學. [17] B. Razavi,李峻霣譯, ”類比CMOS積體電路設計,”滄海書局,中華民國九十三年一月. [18] N. H. E. Weste, K. Eshraghian,黃淑娟譯, ”CMOS VLSI設計原理,” 偉明圖書有限公司,中華民國九十一年十一月. [19] 沈祐民, ” Multilevel Sensing and Verifying Circuit for Flash Memory,” 2004年碩士論文,中興大學. [20] Neil H.E Weste, David Harris "CMOS VLSI DESIGN-Circuit and System Perspective," Third Edition [21] Vladimir Stojanovic and Vojin G. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE J. solid-state circuits, vol. 34,April 1999.
摘要: 
近年來,嵌入式的記憶體架構,已被廣泛的應用在各種不同的系統上,而在密度、功率消耗以及記憶體容量上,必須不斷的提高效能。而嵌入式的記憶體系統,設計重點在於是否能跟記憶體系統以外的電路,整合在相同的製程上。如果能使用相同的製程,而又不需要增加額外的光罩,不論在設計或是製造上,都會節省相當多的時間與成本。本論文的研究目標,是利用標準0.35μm CMOS製程的Single-Poly EEPROM記憶體結構來達到高密度與低成本,並且實現多階判讀的目標,讓單一個記憶體元件,能夠儲存更多位元的資料,以便應用於嵌入式系統。
主要目標為設計出嵌入式EEPROM系統,以便能直接應用於系統晶片(SOC)中。而整個系統包括了記憶體陣列、位置解碼電路、電壓選擇與驅動電路、參考電壓切換電路以及控制時脈產生電路。在功能方面,則有寫入、抹除與讀取三種功能,單一次的寫入或抹除時間在1ms以內完成,並且在每0.25ms間,讀取一次,以判斷是否寫入或抹除成功,每次讀取驗證的時間為100ns;而單純讀取的時間為300ns,可把記憶體元件中所儲存的資料讀取出來。整體系統的平均消耗功率為1.44mW,並使用TSMC 0.35μm COMS 2P4M製程模擬及下線。

In recent years, the embedded storage devices have already been extensively applied to different systems. The density, power consumption and capacity are continually improved to enhance the performance. The key issue of embedded memory is to integrate the other circuit with the memory array in the same process technology without extra masks. That will save a lot of time and cost in design and manufacture. The goal of this thesis is utilizing standard 0.35μm CMOS technology to design multilevel sensing and verifying circuit of embedded EEPROM to achieve high density and low cost due to one memory cell storing more than one bit.
The primary purpose is to design an embedded EEPROM system for applications to systems on a chip (SOC). The complete system includes memory arrays, address decoders , voltage selection and voltage driver circuits, reference voltage switch circuits and control signal generatosrs. There are three major functions, which are programming, erasing and reading. The time for programming or erasing is about 1ms with reading/verifying time of 100ns every 0.25ms. For read-only operation, the reading time is 300ns to access the data form the memory. Average power consumption of chip is 1.44mW. The complete system has been simulated , fabricated and measured using TSMC 0.35μm CMOS 2P4M technology.
URI: http://hdl.handle.net/11455/8159
其他識別: U0005-1908200815082500
Appears in Collections:電機工程學系所

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