Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8171
標題: 依實際IP長度有效分配記憶體之路由器設計
Design of Router Memory with Efficient Distribution for Prefix Length
作者: 涂嘉良
關鍵字: Router;路由器;Skip array;跳躍陣列
出版社: 電機工程學系
摘要: 
現今在高執行的路由器中,網路位址的查尋是主要的瓶頸,尤其是當網路速度高達每秒數十億位元時。IP的位址查尋是一種挑戰,因為它需要最長前端吻合。除此之外,路由表容量的大量増加和高速網路的連接都增加了路由器的困難度。在這個論文中對於查尋、新增和刪除,我們利用了以前基本的架構,再參考實際網路的IP位址分佈圖,將記憶體有效的放在IP位址所佔據的長度內。再者我們擴大跳躍的功能,利用這些技術更進一步節省記憶體的空間,在此我們使用硬體描述語言進行此方法的硬體設計,並且以同步的0.35μm之SRAM做為其位址存放的記憶體,在硬體管線方式下於每次的記憶體存取後即有查尋結果的輸出。經由記憶體分配的模擬結果,雖然增加14%的體憶體空間,但卻增加了62%可使用的輸出埠。

With high-speed multi-gigabit links required in the Internet , the lookup becomes a great bottleneck. The routing table lookup needing longest prefix matching is a challenge. Beside, the large capacity of lookup table and high-speed links increase the difficulty of IP router. In this thesis, a lookup scheme based on a previous structure and the real IP address length is proposed, which can efficiently handle IP routing lookup, insertion, and deletion inside the routing table. We use the skip function to reduce the memory space. Hardware design of the routing table was carried out using the Verilog hardware description language. It uses the synchronous 0.35μm SRAM as the router memory. In a hardware pipeline configuration, the output port is obtained in every memory access. We increase 62% of usable output port, with increase of 14% memory space.
URI: http://hdl.handle.net/11455/8171
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.