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Design of Low Power Low Density Parity Check Code Decoder
|關鍵字:||Decoder;解碼器;Low power;High throughput;低功率;高傳輸速度||出版社:||電機工程學系所||引用:|| Simon Haykin, “Communication Systems 4th Edition,” John Wiley & Sons, Inc.  R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21–28, Jan. 1962.  C. E. Shannon, “A Mathematical Theory of Communication,” Bell System Technical Journal, vol. 27, pp. 379-426, 623-656, July, October, 1948.  Thomas J. Richardson and Rudiger L. Urbanke, “Efficient Encoding of Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp.638 – 656, Feb 2001  Xiao-Yu Hu, Evangelos Eleftheriou, Dieter-Michael Arnold, and Ajay Dholakia, “Efficient Implementations of the Sum-Product Algorithm for Decoding LDPC Codes,” IEEE Global Telecommunications Conference, pp.1036-1036E, 2001  Jin Lu Membe and José M. F. Moura, “Partition-and-Shift LDPC Codes” IEEE Transactions on Magnetics, vol. 41, no. 10, October 2005  Artisan Standard Library Register File Generator User Manual  Shu Lin, J. Daniel, Jr. Costello, “Error Control Coding Fundamentals and Applications,” New Jersey, NJ: Prentice-Hall, 1983.  Sang-Min Kim and Keshab K. Parhi, “Overlapped decoding for a class of quasi-cyclic LDPC codes,” IEEE Signal Processing Systems (SIPS 2004), pp.113-117, 2004.  A. Blanksby and C. Howland,“A690-mw1-Gb/s 1024-b,rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404–412, Mar. 2002  Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Member, IEEE,Yar-Sun Hsu, and Shyh-Jye Jou, “An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 3, March 2008  Ahmad Darabiha, Anthony Chan Carusone and Frank R. Kschischang “Power Reduction Techniques for LDPC Decoders”, IEEE J. Solid-State Circuits, vol. 43,no. 8,pp.1835-1845,Aug 2008  林彥志, “低功率低密度同位元查核碼解碼器設計”, 2007年碩士論文, 國立中興大學。  Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang and Chen-Yi Lee, “A 3.33Gb/s(1200,720) Low-Density Parity Check Code Decoder,” Proc. of European Solid-State Circuits Conference, pp. 211-214, 2005  Sang-Min Kim; Parhi, K.K., “Overlapped decoding for a class of quasi-cyclic LDPC codes,” IEEE Signal Processing Systems, pp. 113-117, 2004.  Hao Zhong and Tong Zhang, “Design of VLSI Implementation-Oriented LDPC Codes,” IEEE Semiannual Vehicular Technology Conference (VTC) , pp.670-673, Oct. 2003  Jeremy Thorpe, “Design of LDPC Graphs for Hardware Implementation,” IEEE International Symp. Information Theory, pp. 483, 2002  Emmanuel Boutillon, Jeff Castura, Frank R.Kschischang, “Decoder-First Code Design,” Proc. of the 2nd International Symposium on Turbo code and Related Topics, Brest, France, pp. 459-462, Sep. 2000  Joachim Hagenauer, Elke Offer, and Lutz Papke, “Iterative Decoding of Binary Block and Convolutional Codes,” IEEE Transactions on Information Theory, vol. 42, no. 2, pp. 429-445, Mar. 1996||摘要:||
本論文提出了一個高傳輸速度的低密度同位查核碼解碼器之硬體設計電路，使用矩陣大小為512×1024、行權重及列權重分別為3、6之規則隨機查核矩陣，在硬體架構上分成四個單元，分別為：變數點單元、查核點單元、記憶體單元及配置單元。記憶單元利用了Artisan 2-Ports Register File加上暫存器架構而成，並經由適當的規劃大幅降低了Register File所需要的個數及面積；查核點單元以min-sum演算法來做為硬體設計原則。
本論文之設計以TSMC 0.18μm CMOS技術合成，在頻率為50MHz、解碼次數為8次時，傳輸速度可達到1.47Gbps，cell area為3.6 (mm2)，功率消耗為297 mW。
In this thesis, a high throughput decoder for Low Density Parity Check Code is presented. The (512, 1024) check matrix is a regular matrix whose column weight and row weight are 3 and 6, respectively. There are 4 units which including a Variable Node Unit (VNU), a Check Node Unit (CNU), a Memory Unit and a Distributor. The Memory Unit is composed of Artisan 2-Ports Register Files and registers. The size of the Register Files was greatly reduced with appropriate arrangement. The Min-sum algorithm was applied in CNU.
During the decoding process of the traditional decoding method, CNU and VNU operations are active alternatively in every decoding iteration. To increase the throughput, these idled CNU and VNU circuit blocks can be utilized more efficiently by using Partition-and-Shift method. Therefore, the throughout is increased to almost two times, and power dissipation can be reduced significantly.
In this thesis, the design was synthesized using TSMC 0.18 μm CMOS technology. It can achieve 1.47 Gbps throughput with 8 iterations in cell area of 3.6 (mm2). The power dissipation is 297 mW at clock frequency of 50MHz.
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