Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8258
標題: 高效能先進加密標準加解密器架構設計與實作
High Performance AES Cipher Architecture Design and Chip Implementation
作者: 張利全
Chang, Li-Chung
關鍵字: AES;先進加密標準;Finite Field;chip;cipher;memory-less;有限場;晶片;密碼;無記憶體
出版社: 電機工程學系
摘要: 
在現今大多數的先進加密標準(AES)硬體架構中,其最重要的部分為位元組取代轉換(SubByte)中的取代表(S-box),但幾乎都是由查表法的方式來實作。因此我們提出了一個新的不需查表法且為擁有高處理量的取代表理論及其硬體架構。此外我們提出了一個快速且具選擇性的硬體架構來合併混行轉換(MixColumn)與反混行轉換(Inverse MixColumn),其只需經過5個互斥或閘的延遲時間。而我們的先進加密標準加解密器為無記憶體之設計,採用了所提出之取代表及快速混行轉換與反混行轉換,在經過了管線化技巧以及在0.25μm CMOS技術下可達到125Mhz的操作頻率,但所花費之邏輯閘數量只約為八萬。根據我們的研究,我們的硬體架構是為第一個包含了加密及解密功能之無記憶體先進加密標準架構。

Many AES hardware architectures have been proposed and implemented, but the critical component, S-box of SubBytes is almost accomplished by lookup table method. So we propose novel high throughput S-box algorithm and hardware architecture without lookup table method. For MixColumn and Inverse MixColumn module, we propose a fast optional module to integrate them and with only 5 XOR gate delay. Furthermore, we implement a memory-less AES cipher with proposed S-box and fast optional MixColumn and Inverse MixColumn module by adopting pipeline method to obtain high throughput under 125Mhz using 0.25μm CMOS technology and the hardware cost is about 80K gate counts. According to our knowledge, our hardware architecture is the first memory-less AES cipher including encryption and decryption function.
URI: http://hdl.handle.net/11455/8258
Appears in Collections:電機工程學系所

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