Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8260
標題: 應用於H.264/AVC之幀內畫面編碼系統分析及電路架構設計與實現
Analysis and Architecture Design of H.264/AVC Intra Frame Coder
作者: 李昆憲
Li, Kun-Hsing
關鍵字: H.264 Intra Frame Coder;H.264幀內畫面編碼器;H.264 Intra Prediction Generator;H.264幀內預測產生器
出版社: 電機工程學系所
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摘要: 
在本篇論文中,我們提出了一個工作於62.5MHz和每秒30張畫面HD720P解析度的8平行度H.264幀內畫面編碼架構。而且我們提出了單一核心之多重轉換架構,可以同時產生整數轉換和Hadamard轉換的結果,來達到減少執行週期與維持影像品質。同時我們在影像編碼的排程上,提出了I4MB/I16MB交錯的排程,來使得硬體使用效率大大的提昇。而在幀內預測架構上,我們使用了種子(seed)運算的方法,使得幀內預測影像可以在2個週期完成4×4影像區塊。在編碼架構上,我們採用了記憶體交錯(Ping-Pong mode)的技術,使得預測階段與編碼階段得以分離,如此才可完成HD720P畫面的編碼。而在基於上下文之可變長度編碼(CAVLC)架構上,我們改善了先前架構過長的掃描週期,採用簡單的邏輯運算,運算出需編碼的位置,使得編碼週期大大的縮短。最後實作結果顯示本架構可工作於62.5MHz的頻率下,完成HD720P@30fps的影像壓縮而晶片面積為1.25×1.25mm2。而且我們架構的模式判斷是採用Hadamard Transfrom的相減轉換絕對值之和(SATD),而且我們的架構有支援I16MB平面模式的預測畫面。若將我們的架構應用於SD(720×480)畫面上的話,我們的架構只需工作於23.4MHz即可完成,因此可以將此電路架構運用於多種影像相關的電子產品上。

In this paper, we proposed an HD720P@30fps H.264 intra frame coder architecture with eight parallel processing elements. And we proposed unique kernel multi-transform architecture, it could generate results of integer transform and Hadamard transform simultaneously, and reach to reduce operation period and keep image quality. In our image coding schedule, we proposed I4MB/I16MB interleaving schedule, to increase hardware utilization. In the intra prediction architecture, we use seed method to operate result of intra prediction, and achieve 4×4 block predictor at two cycles. In the entropy coding architecture, we adopted memory interleaving technology to separate prediction phase and coding phase, and it could achieve HD720P frame coding. In CAVLC architecture, we improve the longer scan period of the previous architecture. Also we utilize simple logic operations to compute the address of coding and reduce the coding period. According to the experimental results, the chip implementation results show that proposed architecture can work at 62.5MHz to achieve HD720P@30fps image compression, and the chip size is 1.25×1.25mm2. In addition, the mode decision of our architecture adopted Hadamard transform (SATD), and our architecture can support prediction frame of I16MB plane mode. If the proposed architecture is applied to the SD(720×480)specification, it can perform 720×480@30fps in real time at 23.4MHz working frequency. Therefore, the proposed architecture can be utilized in various mobile video applications.
URI: http://hdl.handle.net/11455/8260
其他識別: U0005-2108200814515500
Appears in Collections:電機工程學系所

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