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標題: 低功率分離位準電荷分享差動邏輯
Low Power Split-Level Charge Sharing Differential Logic
作者: 王義豪
Wang, I-Hao
關鍵字: differential logic;差動邏輯;low power;charge sharing;低功率;電荷分享
出版社: 電機工程學系
可攜式行動系統運算功能需求量日益強大,包括運算功能與使用時間不斷的提昇,高複雜度的邏輯電路設計方法是無法避免的。因此,在高複雜度的邏輯電路中可用差動邏輯(Differential Logic)的設計方法實現。本論文比較各種不同差動邏輯對於散入(fan-in)的比較,並提出一個新型的差動邏輯架構,使用能量回收的技術以降低差動邏輯在預充電期間(precharge phase)的消耗功率。經由模擬一個八位元的前瞻進位加法器可得知我們所提出的分離位準電荷分享差動邏輯(SCSDL)可比動態串接電壓切換邏輯(DCVSL)減少31.207%的消耗功率。

Due to the increasing demand for high computational power and reliability of portable mobile system, a high complex logic design technique is indispensable. Therefore, complex gates with high fan-in can be implemented using differential logic design techniques. In this thesis, we compare several differential logic with various of fan-in number, and propose a new kind of differential logic structure, which uses an energy recycling technique to reduce power dissipation of differential logic at the precharge phase. Simulation results of an 8-bit Carry-Lookahead adder show that the proposed Split-Level Charge Sharing Differential Logic can reduce 31.207% power dissipation compared to Dynamic Cascode Voltage Switch Logic dissipation.
Appears in Collections:電機工程學系所

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