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標題: 適用於H.264之內文可調適性算術編碼器架構設計與實現
Design and Implementation of Context Adaptive Binary Arithmetic Coder in H.264
作者: 萬佳明
Wan, Chia-Ming
關鍵字: H.264;可調適性算術編碼;CABAC;Arithmetic Coding;硬體架構
出版社: 電機工程學系所
引用: [1] D.Marpe, H.Schwarz, and T. Wiegand, “Context-Based Adaptive Binary Arithmetic in the H.264/AVC Video Compression Standard,” IEEE Transactions on Circuits and Systems for Video Technology,VOL.13,NO.7,July 2003. [2] R. R. Osorio and J.D. Bruguera, “Arithmetic Coding Architecture for H.264/AVC CABAC Compression System,” Euromicro Symposium on Digital System Design, pp. 62-69, 31 Aug.-3 Sept. 2004. [3] R. R. Osorio and J.D. Bruguera,“ A New Architecture for Fast Arithmetic Coding in H.264 Advanced Video Coder,” Euromicro Symposium on Digital System Design, pp.298-305, 30 Aug.-3 Sept. 2005.Video Codec for Audiovisual Services at px64Kbit/s, ITU-T Recommendation H.261, Mar.2005. [4] Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbit/s - Part2: Video, ISO/IEC 11172, 1993. [5] Information Technology - Generic Coding of Moving Pictures and Associated Audio Information : Video, ISO/IEC 13818-2 and ITU-T Rec.H.262,1996. [6] Information Technology - Coding of Audio - Visual Objects - Part2 : Visual,ISO/IEC 14496-2,1999. [7] H. Shojania and S. Sudharsanan, ”A High Performance CABAC Encoder,” IEEE-NEWCAS Conference, 2005, pp. 104 - 107, June 2005. [8] Lingfeng Li,Yang Song,Takeshi Ikenaga,and Satoshi Goto, , “A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile”, IEEE APCCAS'06, pp. 761-764, Singapore, Dec. 2006. [9] O.Flordal,D.Wu,and D.Liu, “Accelerating CABAC encoding for multi-standard media with configurability,”in Proc. Of IPDPS,2006. [10] A high throughput binary arithmetic coding engine for h.264/avc Solid-State and Integrated Circuit Technology, 2006. ICSICT ''06. 8th International Conference [11] Joint Video Team, Draft ITU-T Recommendation and Final Draft InternatioStandard of Joint Video Specification, ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC,May 2003. [12] C. C. Kuo and S. F. Lei, “Design of a Low Power Architecture for CABAC Encoder in H.264,” IEEE APCCAS 2006, pp.243-246, 4-7 Dec. 2006. [13] R. R. Osorio and J. D. Bruguera, “High-Throughput Architecture for H.264/AVC CABAC Compression System,” IEEE Trans. Circuits Syst. Video Technol., Vol. 16, Issue 11, pp.1376-1384, Nov. 2006. [14] ISO/IEC JTC1/SC29/WG1 N1855, JPEG 2000 Part I: Final Draft International Standard (ISCAS) ,2000,pp.299-302. [15] ISO/IEC JTC1/SC29/WG1,JBIG2 Final Draft Standard,July 1999. [16] Oskar Flordal,Di Wu,and Dake Liu, Accelerating CABAC Encoding for Multi-standard Media with Configurability Proceeding of IEEE IPDPS06 (Reconfigurable Architectures Workshop (RAW)),1999. [17] M.Dyer, D. Taubman, and S. Nooshabadi, “Improved throughput arithmetic coder for JPEG2000,”in Proc. Of ICIP,2004. [18] P. S. Liu, J. W. Chen, and Y. L. Lin, “A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H.264 Advanced Video Coding,” IEEE VLSI-DAT 2007, pp.1-4, April 2007. [19] G.Pastuszak, “A high-performance architecture of arithmetic coder in JPEG2000,”in Proc. Of ICME,2004. [20] L. Li, Y. Song, et al., “Hardware Architecture Design of CABAC Codec for H.264/AVC”, IEEE VLSI-DAT'07, pp.248-25, Hsinchu, Taiwan, April 2007. [21] J. L. Chen, Y. K. Lin, and T. S. Chang, “A low cost context adaptive arithmetic coder for H.264/MPEG-4. AVC video coding,” in IEEE Int. Conf. on Acoustics,2007. [22] Y. J. Chen, C. H. Tsai, and L. G. Chen, "Analysis and architecture design for multi-symbol arithmetic encoder in H.264/AVC," VLSI Design/CAD Symposium 2005, Aug. 2005 [23] Jose L.Nunez-Yanez, Vassilios A. Chouliaras: Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP 2005: 411-416C. [24] Transactions on Circuits and Systems for Video Technology., vol. 11, no. 7, pp. 890-897, July 2001. [25] Y.W.Chang, H.C.Fang,and L.G.Chen, “High performance two-symbol arithmetic encoder in JPEG 2000,”in Proc. of ISCE,2004.
在本論文中,我們提出了一個六套可調適性算術編碼器同時平行處理的架構。為了達到名副其實的6-symbol的結果,在調適模型方面,我們以暫存器取代了記憶體其目的就是要為了解決資料依存性(Data dependency)問題。除此之外,我們簡化演算法中的部份算式以較為節省硬體的電路取代,且設計出來的重新正規化(Renormalization)電路在一個時脈週期內即可計算完畢,充分地減少了計算一張畫面所需的時間。

CABAC在高階視訊編碼器最大的瓶頸是在於由於循序處理造成資料依存性(Data Dependency)非常的高。因此,我們為了想知道每個巨觀區塊最大的symbol數為多少先進行一連串的模擬,然後我們做出一套1-symbol的CABAC編碼器,再依照模擬所得出的數據決定要做多少個平行處理的架構。最後,我們的6-symbol架構可以改善成在一秒鐘內可以處理750Msymbol數,跟文獻[22]一樣,是目前為止throughput最高的架構。除此之外,我們也改善部份H.264的演算法,使我們的算術編碼器節省晶片面積。

實作結果顯示,本架構可工作於125MHz,而晶片的面積為1.18*1.18 mm2。可應用於4SVGA (1600x1200),每秒30張的畫面上,如果是處理1280*720的畫面,則只需要62.5Mhz即可實現。因此可以將此電路架構應用相關電子產品之上。

In this paper, a parallel 6-symbol Context-Adaptive Binary Arithmetic Coding Architecture is proposed. In context model, in order to solve data dependency, we replace memory with register. In addition, we simplify partial algorithm in H.264 standard.Our renormalization circuit can be done in one cycle while calculating corresponding values for a symbol and saving the execution time.
The bottleneck of CABAC is on high data dependency of recursive arithmetic coding. Therefore, we first simulate the maximum symbols per macroblock. Then, we propose a one-symbol arithmetic encoder. Finally, we will present a multi-symbol architecture according to the most symbols per macroblock. Our multi-symbol architecture can process 750 Msymbols per second and work at 125MHZ. Thus, it can achieve the highest throughput in all architectures. The throughput rate is the same as [22].
The chip has been implemented using TSMC 0.18 um 1P6M. Its area size is 1.18x 1.18 mm2. According to the experimental results, the proposed architecture can process 1600 x 1200 and 1280 x 720 resolution pictures in 30 frames per second at 125 MHz and 62.5 MHz, respectively. Therefore, our proposed architecture can be utilized in many mobile video applications.
其他識別: U0005-2108200814581800
Appears in Collections:電機工程學系所

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