Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8286
標題: 適用於H.264/AVC之管線化內文可調適性算術解碼器架構設計與實現
Design and Implementation of Pipelined CABAC Decoder for H.264/AVC
作者: 王宜川
Wang, Yi-Chuan
關鍵字: 算數解碼;CABAD
出版社: 電機工程學系所
引用: [1]. ITU-T Recommendation and International Standard of Joint Video Specification (ITU-T Rec.H.264/AVC, ISO/IEC 14496-10) [2]. The H.264/AVC JM Reference Code, the last version is available on the web site: http://iphome.hhi.de/suehring/tml/download/ [3]. D.Marpe, H.Schwarz, and T. Wiegand, “Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard” IEEE Trans. on Circuits and Syst. for Video Technology, VOL.13, NO.7, July 2003. [4]. Wei Yu and Yun He, “A high performance CABAC decoding architecture”, IEEE Trans. on Consumer Electronics, Volume 51, Issue 4, Nov. 2005 Page(s):1352 - 1359 [5]. Chung-Hyo Kim, and In-Cheol Park, "High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction" IEEE Symp. on Circuits and Syst., ISCAS 2006 Proceedings, 21-24 May 2006 Page(s):4 pp. [6]. Eeckhaut, H., Christiaens, M., Stroobandt, D., and Nollet, V., "Optimizing the critical loop in the H.264/AVC CABAC decoder", IEEE International Conf. on Field Programmable Technology, FPT 2006. ,Dec. 2006 Page(s):113 - 118 [7]. Peng Zhang, Wen Gao, Don Xie, and Di Wu, "High-Performance CABAC Engine for H.264/AVC High Definition Real-Time Decoding", International Conf. on Consumer Electronics, ICCE 2007. Digest of Technical Papers. 10-14 Jan. 2007 Page(s):1 - 2 [8]. Yi, Y. and Park, I.-C., "High-Speed H.264/AVC CABAC Decoding", IEEE Trans. on Circuits and Systs. for Video Technology, Volume 17, Issue 4, April 2007 Page(s):490 - 494 [9]. Yan Zheng, Shibao Zheng, Zhonghua Huang and Ziliang Zhao, "A Time and Storage Optimized Hardware Design for Context-Based Adaptive Binary Arithmetic Decoding in H.264/AVC", IEEE International Conf. on Multimedia and Expo, 2-5 July 2007 Page(s):1567 - 1570 [10]. Jian-Wen Chen and Youn-Long Lin, "A High-Performance Hardwired CABAC Decoder", IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2007. Volume 2, 15-20 April 2007 Page(s):II-37 - II-40 [11]. R. R. Osorio and J. D. Bruguera, “High-Throughput Architecture for H.264/AVC CABAC Compression System,” IEEE Trans. On Circuits and Syst. for Video Technol., Vol. 16, Issue 11, pp.1376-1384, Nov. 2006. [12]. R. R. Osorio and J.D. Bruguera,“ A New Architecture for Fast Arithmetic Coding in H.264 Advanced Video Coder,” Euromicro Symposium on Digital System Design, pp.298-305, 30 Aug.-3 Sept. 2005.Video Codec for Audiovisual Services at p64Kbit/s, ITU-T Recommendation H.261, Mar. 1993. [13]. R. R. Osorio and J.D. Bruguera, “Arithmetic Coding Architecture for H.264/AVC CABAC Compression System,” Euromicro Symposium on Digital System Design, pp. 62-69, 31 Aug.-3 Sept. 2004. [14]. Mo Li and Wuchen Wu, “A high throughput binary arithmetic coding engine for h.264/avc”, Solid-State and Integrated Circuit Technology, 2006. ICSICT ''06. 8th International Conference [15]. Oskar Flordal, Di Wu, and Dake Liu, Accelerating CABAC Encoding for Multi-standard Media with Configurability Proceeding of IEEE IPDPS06 (Reconfigurable Architectures Workshop (RAW)),1999. [16]. Lingfeng Li,Yang Song, Takeshi Ikenaga, and Satoshi Goto, , “A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile”, IEEE APCCAS'06, pp. 761-764, Singapore, Dec. 2006. [17]. H. Shojania and S. Sudharsanan, ”A High Performance CABAC Encoder,” IEEE-NEWCAS Conference, 2005, pp. 104 - 107, June 2005. [18]. O.Flordal, D.Wu, and D.Liu, “Accelerating CABAC encoding for multi-standard media with configurability” in Proc. Of IPDPS,2006. [19]. C. C. Kuo and S. F. Lei, “Design of a Low Power Architecture for CABAC Encoder in H.264,” IEEE APCCAS 2006, pp.243-246, 4-7 Dec. 2006. [20]. P. S. Liu, J. W. Chen, and Y. L. Lin, “A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H.264 Advanced Video Coding,” IEEE VLSI-DAT 2007, pp.1-4, April 2007. [21]. L. Li, Y. Song, et al., “Hardware Architecture Design of CABAC Codec for H.264/AVC”, IEEE VLSI-DAT'07, pp.248-25, Hsinchu, Taiwan, April 2007. [22]. J. L. Chen, Y. K. Lin, and T. S. Chang, “A low cost context adaptive arithmetic coder for H.264/MPEG-4. AVC video coding,” in IEEE Int. Conf. on Acoustics,2007. [23]. Y. J. Chen, C. H. Tsai, and L. G. Chen, "Analysis and architecture design for multi-symbol arithmetic encoder in H.264/AVC," VLSI Design/CAD Symposium 2005, Aug. 2005 [24]. Jose L.Nunez-Yanez, Vassilios A. Chouliaras: Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP 2005: 411-416C.
摘要: 
新的H.264/AVC標準在大部分的影片解析度與流量下,與先前的標準比較提供高達50%的壓縮增益。然而,解碼器所需複雜度大約是MPEG-2與MPEG-4 Visual Simple Profile的四倍!一些H.264/AVC提供的主要工具必須為此負責,包含可變區塊大小、哈達碼轉換、RD-拉格蘭吉最佳化、B畫面、1/4精度位移向量、增加的搜尋區域和參考畫面,與當然的本論文主角—CABAC。內容可適應性二位算數編碼器 (CABAC) 是H.264/AVC中提供的其中一項熵編碼,與其他內容可適應性可變長度編碼比較,CABAC承擔25%~30%的存取頻率負擔,但輸出編碼流量大約可減少16%。本論文提供一高效能、全管線化、解決資料相依性的CABAC解碼器,並且運作高達200MHz,相較其他舊設計兩倍以上的效能。

Context Adaptive Binary Arithmetic Coding (CABAC) is one of the two alterna-tive entropy coding method specified in H.264/AVC. Compared with other tech-niques like Context Adaptive Variable Length Coding (CAVLC), CABAC brings access frequency increase from 25% to 30% with bit rate reduction up to 16%. In this thesis, we propose a high-performance and full-pipelined CABAC decoder without data dependency. And it can run at 200 MHz and have twice throughput of the fastest one of the previous works.
URI: http://hdl.handle.net/11455/8286
其他識別: U0005-2108200819213800
Appears in Collections:電機工程學系所

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