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Voltage Control Oscillator Design For Ultra-Wideband Wireless LAN Application.
|關鍵字:||壓控振盪器;VCO;正交壓控振盪器;鎖相迴路;QVCO;PLL||出版社:||電機工程學系所||引用:||Ian Oppermann, Matti Hämäläinen and Jari Iinatti, UWB Theory and Applications. John Wiley & Sons, Inc. 2004. S. A. Ghorashi, B. Allen, M. Ghavami and A. H. Aghvami, “An overview of MB-UWB OFDM,” Ultra Wideband Communications Technologies and System Design, pp.107-110, July 2004. D. M. W. Leenaerts,“Transceiver design for multiband OFDM UWB,” EURASIP Journal on Wireless Communacations and Networking, Article ID 43917, vol. 2006, pp.1-8,Jan 2006. B. Razavi,T. Aytur,C. Lam,F. R. Yang,K. Y. Li,R. H. Yan,H. C Kang, C. C. Hsu and C. C. Lee, “A UWB CMOS transceiver,” IEEE Journal of Solid-State Circuits, vol.40, no.12, pp.2555-2562, Dec. 2005. T. H. Lee,The Design of CMOS Radio-Frequency Integrated Circuits, New York Cambridge University Press, 1998. D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE Journal of Solid-State Circuits, vol.36, no.6, pp.896-909, June 2001. D. B. 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Hong, “A 5GHz CMOS monolithic fractional-N frequency synthesizer,” IEEE International Conference on ASIC, vol.2, pp.626-629, Oct 2005 B. Razavi, Design of Analog CMOS Integrated Circuits, McGRAW-HILL, 2000 J.Gibbs and R.Temple, “Frequency domain yield its data to phase locked synthesizer,” Electronics, pp.107-113, April 1978 T. Ishioka, M. Ueno, T. Nakazawa, T. Watanabe, Y. Oida and Y. Tokumaru Toshiba corporation, Semiconductor Division, “An ultra low power 500MHz dual modulus prescale”, IEEE Consumer Electronics, vol.3, pp.568-575, Aug 1985||摘要:||
本論文以實現應用於超寬頻無線收發機內之本地振盪信號源產生電路為主；探究相關電路設計上可能遇到的問題，並實際製作出晶片加以驗證。我們使用的是國家實驗研究院晶片系統中心所提供之TSMC 0.18μm 1P6M CMOS 1.8V供應電壓製程；總共製作出兩種不同的壓控振盪器及一個完整的除整數型鎖相迴路。本論文整體將以這三塊電路為主架構，分成三個章節來講述各別之電路原理、模擬結果和最後的晶片量測結果。
This thesis mainly regards the realization of the local oscillation circuitry for the UWB wireless transceiver application. We probed into problems which may be encountered in the relevant circuit design and actually fabricated chips for verification. There are two kinds of different oscillators will be explored and we also finished one complete phase lock loop. All the chips have already been implemented in the TSMC 0.18μm 1P6M CMOS process using 1.8V supply voltage which is provided by National Chip Implementation Center (CIC). According to these three chips, this thesis also divides into three major parts. Each chapter includes principles of circuit design, simulation results and measurement results.
In chapter two, we adopt discrete tuning by using switched inductors in the cross-couple pair VCO, and the tuning frequency range of the finished chip can cover UWB band 1, 2 and 3. The concept of our circuit is to combine the varactors and the switched inductors which result in two frequency bands to enlarge the tuning range of the VCO. Simulation result shows that the tuning range can reach the 2GHz (3GHz to 5GHz) requirement, and the phase noise is lower then -120dBc/Hz at 1MHz frequency offset. The measurement result shows that the best phase noise is about -108 dBc/Hz at 1MHz frequency offset when the oscillating frequency is 3.186 GHz.
In chapter three, we adopt discrete tuning by using switched capacitors in the back-gated QVCO, and the tuning frequency range of the finished chip can also cover UWB band 1, 2 and 3. In order to reach higher tuning range, we just added two sets of switching capacitors in the LC tank. The characteristic of the back-gated QVCO circuit is low phase noise and low power consumption. It is shown from the simulation results that the tuning range is also from 3GHz to 5GHz. The phase noise is lower then -120dBc/Hz at 1MHz frequency offset, and the total power consumption is 10.8mW. The measurement result shows that the best phase noise is about -105.41dBc/Hz at 1MHz offset when the oscillating frequency is 4.751 GHz.
In chapter four, a 802.11a low band dual-modulus phase lock loop is implement by adopting back-gate QVCO which is designed in the previous chapter. The locking frequency of the PLL is around 5.14 GHz to 5.72 GHz. The locking time is lower then 5μs, and the best peak-to-peak jitter can lower than 48.5ps.
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