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2-D Simulation of the Small-Signal Circuit Parameters Analysis and Large-Signal Behavior for GaAs MESFET's
本論文以二維元件模擬對均勻摻雜砷化鎵(GaAs)場效電晶體進行研究。元件模擬主要以self-consistent 的方式來解基本的支配電晶體運作的方程式並分別得到載子濃度及電勢能的解。由此我們針對數個砷化鎵(GaAs)場效電晶體的不同結構進行小訊號及大訊號行為的模擬。在萃取元件參數的過程中我們使用軟體上”Cold FET”的方法來萃取外部的源極與汲極電阻。內部電路參數可經由內部Y參數計算結果轉換之後獲得。我們顯示均勻摻雜砷化鎵(GaAs)場效電晶體內部電路參數對汲極電壓的萃取結果。我們以二維模擬對寬凹形(wide recess)與窄凹形(narrow recess)砷化鎵(GaAs)場效電晶體的閘極-汲極崩潰電壓仔細研究。其結果顯示電壓崩潰發生在閘極靠汲極的邊緣。元件設計參數與電路參數之間的關係可經由本篇論文所提到的方法來確立。
2-D semiconductor device simulations are used to study uniform doped GaAs MESFETs in this thesis. The primary function of simulations is to solve the basic governing equations in a self —consistent way and obtain the electrostatic potentials and carrier concentrations, respectively. Thus, several GaAs MESFETs with different structure have been simulated for both small-signal and large-signal behavior. A “software” cold FET method is incorporated into the de-embedding process to extract the extrinsic source and drain resistance. Intrinsic circuit parameters are then converted from the calculated intrinsic Y parameters. Circuit parameters as a function of bias voltages for uniform doped MESFETs are presented. The gate-drain avalanche breakdown was studied in detail by performing 2-D numerical simulations of narrow and wide recessed-gate MESFETs. These simulation demostrated that the breakdown occurs at the drain-side edge of the gate. The relations between device design parameters and circuit parameters can be established by using the approach in the thesis.
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