Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8357
標題: 具有頻率校正技術的時脈與資料回復電路
Design of a Clock and Data Recovery Circuit with a Frequency Calibration Technique
作者: 胡啟邦
Pong, Wu-Kai
關鍵字: Frequency Calibration;頻率校正;Clock and Data Recovery;CDR;GPON;Phase Lock Loop;PLL;Fractional-N;時脈與回復電路;被動網路;鎖相迴路;可除小數的鎖相迴路
出版社: 電機工程學系所
引用: [1] C.-K. Yang and M. Horowitz,"A 0.8 um CMOS 2.5 Gbps oversampling receiver and transmitter for serial links,” IEEE Journal of Solid-State Circuits, vol. 31, Dec. 1996 [2] S.-C. Hwu, “Burst-Mode Clock and Data Recovery Circuit for Passive Optical Networks,” M.S. Thesis, National Taiwan University, July 2005 [3] Azita Emami-Neyestanak, “Design of CMOS Receivers for Parallel Optical Interconnects,” Ph.D. Dissertation, Stanford University, August 2004. [4] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003. [5] G. Kramer, G. Pesaventom, Alloptic, Inc., “Ethernet Passive Optical Network(EPON): Building a Next-Generation Optical Access Network,” IEEE Communications Magazine, Topics in LIGHTWAVE, pp. 66-73, Feb. 2002. [6] S. yamashita, S. Ide, K. Mori, A. Hayakawa, N. Ueno, and K. Tanika, “Novel Cell-AGC Technique for Burst-Mode CMOS Preamplifier With Wide Dynamic Range and High Sensitivity for ATM-PON System,” IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 881-886, July 2002 [7]“G.984.2 Gigabit-capable passive optical networks (GPON): Physical media dependent (PMD) layer,” ITU-T, 2003.IEEE 802.3ah Draft Standard, July 2003. [8] B. Razavi, “Challenges in the design of high-speed clock and data recovery circuits,” IEEE Comm. Mag., Aug. 2002. [9] M.S. Yuan, “CMOS timing recovery for SONET OC-3,” M.S. Thesis, National Taiwan University, 2000. [10] .-P. Chen, “Design and Implementation of a 3.125Gb/s Clock Data Recovery Circuit,” M.S. Thesis, National Taiwan University, June 2003. [11] T. Savoj, B. Razavi, High-speed CMOS circuits for Optical Receivers” Kluwer Academic Publishers, 2001 [12] B. Razavi, Y. Ota, R. G. Swarz, “Design Techniques for Low-Voltage High-Speed Digital Bipolar Circuits,” IEEE Journal of Solid-State Circuits, vol. 29, pp. 332-339, March 1994. [13] Floyd M. Gardner, Phaselock Techniques, 3rd edition, New York: Wiley& Sons, 2005. [14] F. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Trans. Communications, Vol. 28, pp. 1849-1858, Nov. 1980. [15] M. Van Paemel, “Analysis of a charge-pump PLL: a new model”, IEEE Trans Communications, Vol.42, pp.2490-2498, July 1994. [16] M. Soyuer and R. G. Meyer, “Frequency limitations of a conventional phase-frequency detector”, IEEE Journal of Solid-State Circuits, Vol. 25, No.8, pp. 1019-1022, Aug. 1990. [17] H. O. Johansson, “A simple precharged CMOS phase frequency detector”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp. 295-299, Feb. 1998. [18] M. Mansuri, D. Liu and C. K. Ken Yang, “Fast frequency acquisition phase-frequency detectors for GSamples/s phase-locked loops”, IEEE Journal of Solid-State Circuits, Vol. 37, No.10, pp. 1331-1334, Oct. 2002. [19] S. O. Jeon, T. S. Cheung and W. Y. Choi, “Phase/frequency detectors for high-speed PLL applications”, Electronic Letters, Vol. 34, pp. 2120-2121, Oct. 1998. [20] B. Razavi, “A Study of Phase Noise in CMOS Oscillators”, IEEE Journal of Solid-State Circuits, Vol. 31, No.3, pp. 331-343, MARCH 1996. [21] N.H.W. Fong, J.-O. Plouchart, N. Zamdmer, Duixian Liu, L.F. Wagner, C. Plett and N.G. Tarr, “Design of wide-band CMOS VCO for multiband wireless LAN applications”, IEEE J. Of Solid-State Circuits, Vol. 38, No.8, pp. 1333-1341, Aug. 2003 [22] Zhenbiao Li and Kennethh K. O., “A Low-Phase-Noise and Low-Power Multiband CMOS Voltage-Controlled Oscillator”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 6, JUNE 2005. [23] S. Keliu and S.-S. Edgar, CMOS PLL Synthesizers: Analysis and Design, Springer, 2005. [24] B. D. Muer and M. Steyaert, CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration, Kluwer Academic Publishers, 2003. [25] A. Hajimiri and T. H. Lee, “A General theory of the phase noise in electrical oscillators”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998. [26] Y. P. Tsivids, Operation and Modeling of the MOS Transistor, McGraw-Hill, 1987. [27] C. Patrick and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 743-752, MAY 199 [28] Y.-T. Chang, “A GFSK Modulator by Using a Fractional-N Frequency Synthesizer”, M. S. thesis, National Taiwan University, 2003
摘要: 
近年來,被動式光纖網路已經被發展使用在數種通訊中,具有快速鎖定資料技術的突發式時脈與資料回復電路為其中一個最重要的電路。本論文中將主要討論可應用在被動式光纖網路,具有頻率校正技術的時脈與資料回復電路,而文章內容主要分成四大部份。
首先,第一部份則是探討一些基本的光纖通訊系統架構、其構成的單元、和被動光纖網路與其規格,從而了解為何需要突發式的時脈與資料回復電路。
第二部分則介紹可除小數的鎖相迴路及三角積分調變器的基本理論以及設計,且會針對一些常用到的相位偵測器、電菏幫浦、壓控掁盪器作分類說明
第三部分,我們提出了一個具有頻率校正技術的時脈與資料回復電路,這電路中包含了可除小數的鎖相迴路、三角積分調變器以及資料回復電路。在這架構中,我們利用了三角積分調變器的特性,當輸入資料速率發生偏移時,能使回復時脈作頻率及相位的改變。而此時脈與資料回復電路是以0.18微米的互補式金氧半製程製造,晶片實際面積為 1.4×1.4mm2。
最後,我們提出了一個可應用在被動式光纖網路並具有頻率校正技術的時脈與資料回復電路,相較於傳統技術,此電路不但能快速鎖定,而且能在資料速率出現偏差時進行時脈校正,使輸出資料不會受頻率偏移影響。而此時脈與資料回復電路是以0.18微米的互補式金氧半製程作模擬,晶片面積為 1.4×1.4mm2

This thesis mainly describes a clock and data recovery circuit with a frequency calibration technique. The thesis will be divided into four parts. The first part of the thesis introduces Optical Network, the specification of the passive optical network and some common used clock and data recovery architectures. Moreover, we also introduces some common used phase detectors and frequency detectors in a clock and data recovery circuit.
The second part of this thesis introduces the fundamentals of fractional-N phase lock loop, introducing the phase frequency detector, the charge pump, the loop filter and the voltage control oscillator. It is because we use a LC oscillator as a voltage control oscillator in the architecture, we introduce the design of a LC oscillator. Furthermore, the fundamental of the Δ-Σ modulator will also be introduced.
The third part primarily introduces a clock and data recovery circuit with a frequency calibration technique. A 2.5-Gb/s oversampling clock and data recovery (CDR) circuit with frequency calibration is realized for optical communication. The CDR circuit contains a fractional-N phase-locked loop (PLL), a delta-sigma modulator (DSM) and a data recovery circuit. The recovered clock is adjusted by the DSM for phase and frequency tuning, incorporating with the phase detector, when the incoming data rate changes. The CDR circuit is implemented with TSMC 0.18-um 1P6M CMOS technology. The simulation results show the proposed CDR circuit recovers the incoming data.
In the last part, we achieve a 2.5Gb/s Gigabit Passive Optical Network (GPON) clock and data recovery circuit with a frequency calibration technique. The CDR circuit is simulated in TSMC 0.18 RF CMOS technology. Its recovery clock frequency is 2.5GHz, the total power is 128mW, the recovery data output jitter is about 18ps, and the total area is 1.4×1.4mm2
URI: http://hdl.handle.net/11455/8357
其他識別: U0005-2508200815435700
Appears in Collections:電機工程學系所

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