Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8370
標題: 隨機動態記憶體位元線讀取之延遲近似解析模型
An Analytical Delay Model for Read Operation on Dynamic Random Access Memory Bit Lines
作者: 施家祥
Shih, Chia-Hsiang
關鍵字: DRAM bit line;隨機動態存取記憶體位元線;interconnect;analytical delay model;distributed RC;相互連接線;延遲解析模型;電阻電容分佈
出版社: 電機工程學系
摘要: 
在要求高密度的極超大型積體電路中,DRAM元件的發展逐漸往深次微米尺寸發展,但元件尺寸的縮小化設計,雖對電路所要求的高密度與高速度達到其標準,但隱約的也帶來了很多問題發生。而這些問題的發生也逐漸影響到電路的性能與原本設計的目標。其中又以interconnect問題對電路效能的影響逐漸嚴重。一般電路設計者對因interconnect造成的延遲效應發生,導致時間或輸出電壓因RC延遲效應估算方式,大多仍採行過去傳統RC延遲模型來估算。然而所使用R與C之數目有限,其準確性逐漸不敷所需,因所佔之總延遲時間漸增,所以在元件尺寸逐漸縮小下,已經失去模型本身對電路模擬的準確度。而發展一套新的RC延遲模型將是必然的趨勢。
本論文之重點即在針對DRAM的位元線電路發展一套新的隨機動態記憶體讀取之近似解析模型,使電路設計者可以透過此簡單的模型,迅速且正確估算出RC延遲效應對DRAM的位元線電路所造成的延遲時間與輸出電壓的變化。而本模型經過與HSPICE(電路模擬軟體)和TMA(元件製造與電性分析模擬軟體)之數值運算後做比較,其準確度皆在容許值以內,且比傳統RC延遲模型大為準確。另外也考慮當字元線以斜坡上升電壓(Ramped Voltage)輸入時,延遲模型的計算方法。而最後也將利用TMA模擬一顆0.18μm DRAM元件,以元件模擬觀點來分析0.18μm DRAM元件電性,且利用所分析的電性,進一步利用TMA的電路模式去驗證所推導模型。
為了真正與由晶片上之實驗數據做比較,本組所設計的DRAM位元線延遲效應測試電路已經透夠華邦電子製造出來,本組人員將繼續完成量測數據與所推導延遲模型進行比對,做最後驗證工作,以確定模型的準確度。

As VLSI circuits migrate to high density, DRAM device technology advances to the deep sub-micron range. The small devices can meet the requirement of the high-speed and high-density, but many other problems degrade circuit performance or even invalidate the original design, especially the interconnect problem influencing the circuit performance is getting more seriously. In general, the circuit designers estimating the delay of interconnect employ the conventional discrete R and C components. Since the numbers of R and C are limited to small numbers, the accuracy is becoming unsatisfied. The interconnect delay occupies the larger percentage of the total delay, so the accuracy of circuit simulation is degraded as the devices are getting smaller, it is necessary to develop a new RC delay model to meet the trend.
The purpose of this thesis is to develop a new analytical delay model for read operation on DRAM bit lines, the circuit designers can use the model to compute the variation of output voltage accurately and quickly on the DRAM bit line with the RC delay effect. The new model was compared with the numerical analysis of the HSPICE (circuit simulation software) and TMA (device/process simulation software). The accuracy between the new model and SPICE simulation / TMA simulation is excellent. It is much more accurate than the conventional discrete RC delay model. In addition, the method to calculate the delay for ramped voltages on the word line was proposed with excellent results, too. Finally, a 0.18μm DRAM device using TMA was simulated to further verify the accuracy of the derived model.
In order to compare with the experimental data on a real chip, a test circuit for DRAM bit line delay is fabricating in Winbond Electronic Inc. Our group will continue to complete the measurement and compare with the derived delay model to certify the accuracy of this new analytical model.
URI: http://hdl.handle.net/11455/8370
Appears in Collections:電機工程學系所

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