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Study of Carrier Transport of Nanoscale Strained NMOSFETs
|關鍵字:||應變;Strained Si:C;金氧半場效電晶體;C-V量測;I-V量測;C-V;I-V||出版社:||電機工程學系所||引用:||Chapter2 References  S.M. Sze. Physics of Semiconductor Devices. 2nd ed. 1981, New York: John Wiley & Sons.  D.K. Schroder, Semiconductor Material and Device Characterization. 1990, New York: John Wiley & Sons.  J. Koomen, "Investigation of the MOST channel conductance in weak inversion," Solid-State Electron., 16,1973, p. 801.  C．G．Sodini, T.W.Ekstedt, and J.L. Moll "Charge accumulation and mobility in the dielecyric MOS transistors,” Solid-State Electron., 25 (9), 1982, p. 833.  P.-M.D. Chow and K.-L. Wang, "A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET''s," IEEE Trans. Electron Devices, 33 (9), 1986, p. 1299.  A.Hairapetian, D. Gitlin, and C.R. Viswanathan, "Low-temperature mobility measurements on CMOS devices," IEEE Trans. Electron Devices, 36 (8), 1989, p. 1448.  C.-L. Huang and G.S. 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split C-V技術可以直接使用在Si:C 金屬氧化半導體元件，量測各種不同的電容構成的特性。從這些電容量，不但可以決定反轉層電荷的電量，而且還可以得到準確的臨界電壓。使用TCAD元件模擬，不同的異質結構元件的電容模型。經由模擬曲線與量測資料的匹配，可以選取價帶與導電帶之間的偏移。
In this dissertation, two important topics are included. One is C-V Measurement Technique for the novel MOS devices. The other is effect of strain on carrier transport of nanoscale MOS devices which has received a lot of attention in the semiconductor industry, recently.
Part I: The split C-V technique was used to measure various capacitance components directly on the Si:C NMOSFET devices. From these capacitances, the inversion charge as a function of gate voltage, as well as the classical device threshold voltage, were determined. The device simulator, TCAD, was used to model the capacitance of the various heterostructure devices. By matching the simulated curves with the measured data, the valence and conduction band offsets between strained-Si and relaxed-SiGe were extracted.
Part II: The strained silicon technology is reviewed and studied. The past several years have witnessed rapid growth in the study of strained silicon due to its potential ability to improve the performance of very large scale integrated circuits. In this work, we investigate the impact of strain effect on carrier transport of NMOSFETs by backscattering theorem. The strain distribution in NMOSFET is simulated by ANSYS. The optimization of 3D device structure in strained Si device has also been studied and discussed in this dissertation.
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