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標題: 高速低電壓差動訊號之傳接器及正比於絕對溫度的參考電壓電路設計
Design of a High Speed LVDS Tranceiver and a PTAT Voltage Reference Circuit
作者: 黃朝彬
Huang, Chao-Bin
關鍵字: LVDS;低電壓差動訊號;High Speed Interface;Voltage Reference;PTAT;高速介面;參考電壓;正比於絕對溫度
出版社: 電機工程學系所
引用: [1] Hedberg M.; Haulin T., “I/O family with 200 mV to 500 mV supply voltage”, IEEE International Solid-State Circuits Conference, pp. 340-341, 1997. [2] R.Goyal, “Managing Signal Integrity”,IEEE Spectrum, pp.54-58, March 1994 [3] “IEEE standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI) ”,IEEE Std. 1596.3, 1996. [4] “Electrical Characteristics of Low Voltage Differential Signaling (LVDS)Interface Circuits,” ANSI/TIA/EIA-644-1995, Telecommunications Industry Association, Nov. 15, 1995. [5] A. Boni, et al, “LVDS I/O interface for Gb/s-per-pin operation in 0.35-um CMOS”, IEEE Journal of Solid-State Circuits, vol. 36, No. 4, pp. 706 -711, April 2001. [6] T. Gabara, et al, “LVDS I/O buffers with a controlled reference circuit,” Tenth Annual IEEE International ASIC Conference and Exhibit, pp. 311 -315, 1997. [7] Jaeseo Lee, et al, “Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections”, IEEE International Symposium on Circuits and Systems, vol.4, pp. 702 -705, 2001. [8] Young, B., “Enhanced LVDS for signaling on the RapidIO/sup TM/ interconnect architecture,” IEEE Conference on Electrical Performance of Electronic Packaging, pp. 17 -20, 2000. [9] P. R. Gray; P. J. Hurst; S. H. Lewis; R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” 4th ed., Wiley, 2001. [10] Behzad Razavi,“Design of Analog CMOS Integrated Circuits”, 2001 [11] Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design” 2nd ed., Oxford, 2002 [12] Hwang-Cherng Chow; Wen-Wann Sheen, “Low power LVDS circuit for serial data communications” Intelligent Signal Processing and Communication Systems, 2005. 13-16 Dec. 2005 Page(s):293 - 296. [13] Y. Jiang and E. K. F. Lee, “Design of low-voltage bandgap reference using transimpedance amplifier,” IEEE Trans. Circuits Syst. II, vol. 47,pp. 552-555, June 2000. . [14] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE J. Solid-State Circuits, vol. 34, pp. 670-674, May 1999. [15] Serra-Graells, F.; Huertas, J.L.; “Sub-1-V CMOS proportional-to-absolute temperature references,” IEEE J. Solid-State Circuits, vol. 38, pp. 84-88, May 2003. [16] A. Buck, C. McDonald, S. Lewis, and T. R. Viswanathan, “A CMOS bandgap reference without resistors,” in Proc. IEEE Int. Solid-State Circuits Conf., 2000, pp. 442-443 [17] H. J. Oguey and D. Aebischer, “CMOS current reference without resistance,” IEEE J. Solid-State Circuits, vol. 32, pp. 1132-1135, July 1997. [18] H. Sanchez, R. Philip, J. Alvarez, and G. Gerosa, “A CMOS temperature sensor for PowerPC™ RISC microprocessors,” in Proc. IEEE Symp.VLSI Circuits, June 1997, pp. 13-14. [19] F. Serra-Graells, “VLSI CMOS subthreshold log companding analog circuit techniques for low-voltage applications,”Ph.D. dissertation, Electron. Dept., Univ. Politècnica Catalunya, Barcelona, Spain, July2001. [20] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” J. Analog Integrated Circuits Signal Process., vol. 8, no. 1, pp. 83-114, 1995. [21] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp.1433- 1440, Oct. 1989. [22] F. Serra-Graells, “VLSI CMOS low-voltage log companding filters,”in Proc. IEEE Int. Symp. Circuits and Systems, vol. I, May 2000, pp.172-175. [23] Stephen H. Hall, James A. McCall, Garret, “High-Speed Digital System Design” Wiley, 2001.
此論文主要研究方向為利用低電壓差動訊號的技術,設計出操作速度可達2Gb/s的傳輸器和接收器。低電壓差動訊號傳接器模擬是使用台積電 TSMC 0.35um 2P4M CMOS 製程。模擬結果顯示傳輸器和接收器操作速度都可達2Gb/s。傳輸器的功率消耗為26.38mW,接收器的功率消耗為16.7mW,佈局面積為455um*455um。

In recent years, the advancement of fabrication and the operation speed of processor becomes faster and faster,and could deal with huger data in unit time. Therefore, it needs a high speed I/O interface for the data transmission between computer peripherals and a variety of application of IC products,Impel I/O interface plays an important role. Low voltage differential signal (LVDS) I/O standard used for data transmission can fulfill the requirements of high speed and low power.

The research of this thesis mainly utilizes low voltage differential signal technology to design 2Gb/s transmitter and receiver. The LVDS circuits are simulations by using TSMC 0.35μm 2P4M CMOS process. Simulate results transmitter and receiver, The chip can operate functionally at 2Gb/s,Transmitter power consumption is 26.38mW,Receiver power consumption is 16.7mW,The chip area is 455μm*455μm.

Otherwise,We provide a PTAT voltage reference circuit,The circuit is composed of MOSFET,Some of MOSFET workd in Subthreshold Region,Because the characteristics,The supply voltage can be lower,To suit in standard CMOS pocess.
其他識別: U0005-2910200814495700
Appears in Collections:電機工程學系所

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