Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8400
標題: 90奈米雙閘極疊接電晶體直流與射頻特性分析
Characterization on DC and RF Performances of Dual-Gate Cascode Transistor in 90-nm CMOS Technology
作者: 官翰傑
Kuan, Han Chien
關鍵字: 雙閘極;Dual-Gatel;疊接電晶體;Cascode
出版社: 電機工程學系所
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摘要: 
本篇論文將介紹射頻積體電路裡常使用的疊接架構電晶體模型,主要重點將放在RF量測特性比較與參數萃取,運用在高頻微波頻段範圍的研究與討論。

雙閘極疊接結構的型態可以提升高頻效能,本文將疊接結構轉化成共用擴散層雙閘極型態(Dual-Gate),並另外提出兩種Layout模式可以降低元件15%的面積,操作在相同偏壓下量測高頻截止頻率、最大的振盪頻率與穩定度來比較特性,在高頻特性下提升了12.2%。Dual-Gate之所以特別之處在於可以使用在多種的電路上,並且可以有較高的增益、較低的雜訊與較小的面積。

本文將針對Dual-Gate模型的小訊號來萃取本質與外部元素,經由公式的計算後,將DC量測與RF量測所得的結果進行分析,並萃取出電容、電阻與電感分別從Y參數與Z參數計算得到,再將萃取出的值帶入模型來對照量測與萃取的曲線是否吻合。為了能夠更了解Dual-Gate就讓我們從本文的研究中來說明。

This thesis investigates the DC, RF performances of a cascode transistor for RF integrated circuit application. The major goal of this thesis concentrates on device characterization and model extraction.
A Dual-Gate cascode is implemented for improving high-frequency performance. The proposed layout shows the reduction of 15% device area in the thesis. Keeping the identical bias condition, measurement result shows that the proposed device has high cut-off frequency and excellent maximum oscillation frequency. The proposed layout shows the improvement of fmax has 12.2% compared with standard layout. Generally, the Dual-Gate transistors are extremely attractive for a variety of application such as the gain control, low noise, small layout area and high breakdown voltage.
In this thesis, a small signal equivalent circuit is proposed to extract the intrinsic and extrinsic elements of Dual-Gate transistor. The initial values are determined from both of the DC and RF measurements during model extraction. The elements of extrinsic capacitance, resistance and inductance are extracted by three-port Y-parameter and Z-parameter calculation from cold measurements. The intrinsic elements of Dual-Gate biased properly are directly extracted from hot measurement. The extracted element values are then optimized to fit the proposed equivalent circuit using the measured three-port S-matrix.
URI: http://hdl.handle.net/11455/8400
其他識別: U0005-3007200817412700
Appears in Collections:電機工程學系所

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