Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8400
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dc.contributor蘇彬zh_TW
dc.contributor裴靜偉zh_TW
dc.contributor.advisor許恒銘zh_TW
dc.contributor.author官翰傑zh_TW
dc.contributor.authorKuan, Han Chienen_US
dc.contributor.other中興大學zh_TW
dc.date2009zh_TW
dc.date.accessioned2014-06-06T06:41:29Z-
dc.date.available2014-06-06T06:41:29Z-
dc.identifierU0005-3007200817412700zh_TW
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J Deen, and C H Chen ”MOSFET Modeling for RF IC Design” IEEE Trans Electron Devices, Vol.52, pp.1286-1303 July 2005 [20]S Lee, C S Kim, and H K Yu ”A Small-Signal RF Model and Its Parameter Extraction for Substrate Effects in RF MOSFETs” IEEE Trans Electron Devices, Vol.48, pp.1374-1379, July 2001 [21]S F Tin, A A Osman, K Mayaram, and C Hu ”A Simple Subcircuit Extension of the BSIM3v3 Model for CMOS RF Design” IEEE J Solid-State circuits, Vol. 35, pp.612-624, Apr.2000 [22]M Je, J Han, H Shin, Kwyro Lee”A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction” Micro electronics Reliability 43 (2003) 601-609. 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Rustagi, J Shi and F Lin”MOSFET Model Extraction Using 50GHz Four-Port Measurements” 2007 IEEE Radio Frequency Integrated Circuits Symposium. [30]J. C. Guo and Y. M. Lin“65-nm 160-GHz ft RF n-MOSFET Intrinsic Noise Extraction and Modeling using Lossy Substrate De-embedding Method” [31]D H Shin and C. P Yue”A Unified Modeling and Design Methodology for RFICs Using Parameterized Sub-Circuit Cells” [32]S Shekhar, J S. Walling and D J. Allstot”Bandwidth Extension Techniques for CMOS Amplidiers” IEEE J Solid-State circuits, Vol. 41,pp.2424-2438, Nov.2006. [33]R Sung, P Bendix, and M B. Das”Extraction of High-Frequency Equivalent Circuit Parameters of Submicron Gate-Length MOSFET’s” IEEE Trans Electron Devices, Vol. 45,pp.1769-1775, Aug.1998 [34]J Brinkhoff, S C.Rustagi, J Shi and F Lin”MOSFET Model Extraction Using 50GHz Four-Port Measurements” Institute of Microelectronics, Singapore 117685. [35]W Wu, S Lam, and M Chan”Effects of Layout Methods of RF CMOS on Noise Performance”IEEE Trans Electron Devices, Vol. 52, pp.2753-2759, Dec.2005. [36]Q Liang, J D. Cressler, G Niu, Y Lu, G Freeman, D C. Ahlgren, R M. Malladi, K Newton, and D L. Harame”A Simple Four-Port Parasitic Demembedding Methodology for High-Frequency Scattering Parameter and Noise Characterization of SiGe HBTs”IEEE Trans Microwave Theory Tech., Vol. 51,pp.2165-2174, Nov.2003 [37]S D WU, G W HUANG, K M CHEN, H C TSENG, T HSU, and C Y CHANG”RF MOSFET Charaterization by Four-Port Measurement”IEICE TRANS. ELECTRON. Vol. E88-C, pp.851-856. May 2005. [38]X Wei, K Xia, G Niu, Y Li, S L. Sweeney, Q Liang, X Wang, S S. Taylor”An Improved On-Chip 4-Port Parasitics De-embedding Method with Application to RF CMOS”IEEE 2007. [39]M. C. A. M. Koolen, J. A. M. Geelen and M. P. J. G. Versleijen”AN IMPROVED DE-EMBEDDING TECHNIQUE FOR ON-WAFER HIGH-FREQUENCY CHARACTERIZATION”IEEE 1991 Bipolar Circuits and Tech. Metting. [40]N. Srirattana, D. Heo, H.M. Park, A. Raghavan, P.E. Allen, and J.Laskar”A New Analytical Scalable Substrate Network Model for RF MOSFET”IEEE 2004. [41]J Han and H Shin”A Scalable Model for the Substrate Resistance in Multi-Finger RF MOSFETs”IEEE 2003. [42]U Mahalingam, S C. Rustagi, and G S. Samudra”Direct Extraction of Substrate Network Parameters for RF MOSFET Modeling Using a Simple Test Structure”IEEE Electron Device Letters, Vol. 27,pp.130-132, Feb.2006 [43]Behzad Razavi”Design of Analog CMOS Integrated Circuits” [44]B. J. Baliga, ”Evolution of MOS-Bipolar power semiconductor technolory”, IEEE Proceedings, Vol.76, pp.409-418, Apr. 1998zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/8400-
dc.description.abstract本篇論文將介紹射頻積體電路裡常使用的疊接架構電晶體模型,主要重點將放在RF量測特性比較與參數萃取,運用在高頻微波頻段範圍的研究與討論。 雙閘極疊接結構的型態可以提升高頻效能,本文將疊接結構轉化成共用擴散層雙閘極型態(Dual-Gate),並另外提出兩種Layout模式可以降低元件15%的面積,操作在相同偏壓下量測高頻截止頻率、最大的振盪頻率與穩定度來比較特性,在高頻特性下提升了12.2%。Dual-Gate之所以特別之處在於可以使用在多種的電路上,並且可以有較高的增益、較低的雜訊與較小的面積。 本文將針對Dual-Gate模型的小訊號來萃取本質與外部元素,經由公式的計算後,將DC量測與RF量測所得的結果進行分析,並萃取出電容、電阻與電感分別從Y參數與Z參數計算得到,再將萃取出的值帶入模型來對照量測與萃取的曲線是否吻合。為了能夠更了解Dual-Gate就讓我們從本文的研究中來說明。zh_TW
dc.description.abstractThis thesis investigates the DC, RF performances of a cascode transistor for RF integrated circuit application. The major goal of this thesis concentrates on device characterization and model extraction. A Dual-Gate cascode is implemented for improving high-frequency performance. The proposed layout shows the reduction of 15% device area in the thesis. Keeping the identical bias condition, measurement result shows that the proposed device has high cut-off frequency and excellent maximum oscillation frequency. The proposed layout shows the improvement of fmax has 12.2% compared with standard layout. Generally, the Dual-Gate transistors are extremely attractive for a variety of application such as the gain control, low noise, small layout area and high breakdown voltage. In this thesis, a small signal equivalent circuit is proposed to extract the intrinsic and extrinsic elements of Dual-Gate transistor. The initial values are determined from both of the DC and RF measurements during model extraction. The elements of extrinsic capacitance, resistance and inductance are extracted by three-port Y-parameter and Z-parameter calculation from cold measurements. The intrinsic elements of Dual-Gate biased properly are directly extracted from hot measurement. The extracted element values are then optimized to fit the proposed equivalent circuit using the measured three-port S-matrix.en_US
dc.description.tableofcontents誌謝 …………………………………………………………………………..i 論文摘要 …………………………………………………………………………..ii Abstract …………………………………………………………………………..iii 目錄 …………………………………………………………………………..iv 表目錄 ………………………………………………………………….………..v 圖目錄 …………………………………………..………………………..….…..v 第一章 緒論 - 1 - 1-1 研究背景及目的 - 1 - 1-2 文獻回顧 - 1 - 1-3 論文架構 - 3 - 1-4 基本微波理論 - 4 - 1-4-1 功率增益方程式 - 4 - 1-4-2 雙埠網路 - 4 - 1-4-3 電路穩定性考量 - 5 - 1-5 CMOS電晶體介紹 - 6 - 1-5-1 導論 - 6 - 1-5-2 CMOS DC物理特性分析 - 6 - 1-5-3 CMOS 高頻特性分析 - 9 - 1-5-4 最大震盪頻率 - 12 - 1-5-5 穩定度判別 - 12 - 第二章 CMOS Dual-Gate電晶體之設計 - 14 - 2-1 CMOS電晶體佈局介紹 - 14 - 2-2 Dual-Gate 佈局介紹 - 15 - 2-3 Dual-Gate Layout 最佳化設計 - 18 - 2-4 DC直流特性分析 - 22 - 2-5 Dual-Gate四種操作區域分析 - 27 - 2-6 C2、C3 Dual-Gate直流特性分析 - 32 - 2-6-1 C1與C2 Dual-Gate DC特性分析比較 - 32 - 2-6-2 C1與C3 Dual-Gate DC特性分析比較 - 36 - 第三章 Dual-Gate電晶體RF特性分析 - 39 - 3-1 簡介 - 39 - 3-2 Dual-Gate模型介紹與分析 - 39 - 3-2-1 4-port De-embedding - 42 - 3-2-2 萃取Extrinsic寄生項 - 44 - 3-2-3 萃取Intrinsic寄生項 - 46 - 3-2-4 寄生效應對高頻特性的影響 - 51 - 3-3 偏壓改變對Intrinsic的變化情形 - 59 - 3-4 量測與模擬對照 - 63 - 3-5 最佳化佈局的RF特性 - 66 - 3-5-1 C1與C2 Dual-Gate RF量測分析 - 66 - 3-5-2 C1與C3 Dual-Gate RF量測分析 - 72 - 3-5-3 結論 - 77 - 第四章 總結 - 78 - 4-1 結論 - 78 - 4-2 未來工作 - 79 - 參考文獻 …………………………………………………………………………- 80 - 表目錄 表2-3-1 C1、C2、C3 Dual-Gate各面積大小 - 22 - 表3-4-1 C1 Dual-Gate 寄生參數值 - 65 - 表3-5-1 C1、C2、C3 Dual-Gate RF特性分析比較 - 77 - 圖目錄 Fig.1-4-1 單級功率放大器反射係數與阻抗示意圖 - 4 - Fig.1-5-1 MOSFET的透視圖 - 7 - Fig.1-5-2 I-V操作區域分析 - 8 - Fig.1-5-3 MOSFET 電流對gm的關係圖 - 9 - Fig.1-5-4 I-V操作區域分析圖 - 9 - Fig.1-5-5 MOSFET高頻小訊號寄生效應 - 10 - Fig.1-5-6 MOSFET小訊號等效電路圖 - 10 - Fig.2-1-1 RFCMOS多指狀元件架構圖 - 14 - Fig.2-2-1 傳統疊接架構Cascode - 15 - Fig.2-2-2 Dual-Gate為改量Cascode架構後,共用相同OD與Guard ring……………………………………………………………….- 16 - Fig.2-2-3 (a)C1 Dual-Gate Layout 示意圖 (b)MultiFinger的 Dual-Gate - 17 - Fig.2-3-1 (a) C2 Dual-Gate Layout示意圖 (b) C2 Dual-Gate Layout 中在Y點多加了Metal 4相連接 - 19 - Fig.2-3-2 C2 Dual-Gate Layout圖 - 20 - Fig.2-3-3 C3 Dual-Gate為使用Minimum rule的Layout示意圖 - 21 - Fig.2-3-4 C3 Dual-Gate Layout - 21 - Fig.2-4-1 (a)(b)分別為不同角度下所看到的Vd-Id電流曲線 ,Vd、Vg1、Vg2從0V增加到2V - 23 - Fig.2-4-2 (a)隨著Vg2電壓的增加,Id電流上升的斜率會有所不同(b)當Vg2增加到1.2V時,gm增加將不會等比例上升 - 24 - Fig.2-4-3 (a)Vg2=0.6 (b)Vg2=0.8 (c)Vg2=1 (d)Vg2=1.2,Vg2在1.2V時飽和區的曲線最平 - 26 - Fig.2-4-4 Vg2愈大Ro阻值愈大 - 26 - Fig.2-5-1 偏壓點名稱 - 27 - Fig.2-5-2 單顆MOS量測出Vd-Id曲線,再將轉換為Dual-Gate曲線 - 28 - Fig.2-5-3 Dual-Gate 的Vd-Id會有四種不同的操作區域 - 29 - Fig.2-5-4 標示出Vg-Id的所有區域 - 30 - Fig.2-5-5 Vg1電壓在1V以上時,Id電流上升比例已不大 - 31 - Fig.2-5-6 四組電流經過這三種區域 - 31 - Fig.2-5-7 相同電流下S-T、S-S、T-S,gm會有不同大小 - 32 - Fig.2-6-1 C1與C2 Dual-Gate(a)Vg-Id電流曲線圖,(b)gm - 33 - Fig.2-6-2 C2 Dual-Gate在Vd-Id的圖中電流比C1 Dual-Gate來的大………………………………………………………………….- 34 - Fig.2-6-3 C1與C2 Dual-Gate OD與Guard ring距離不同,使Rsub電阻較大 - 34 - Fig.2-6-5 dv的距離將影響Rsub電阻 - 35 - Fig.2-6-6 C1與C3 Dual-Gate比較(a)C3 Dual-Gate電流不受OD面積縮小而電流變小(b)gm - 37 - Fig.2-6-7 C1與C3 Dual-Gate Vd-Id電流相差不大 - 37 - Fig.3-2-1 Dual-Gate 的小訊號將比Cascode更為簡化 - 40 - Fig.3-2-2 (a)疊接架構Cascode小訊號模型 (b)Dual-Gate小訊號模型………………………………………………………………….- 41 - Fig.3-2-3 4port元件的De-embedding (a)元件(b)OPEN為扣除電容(c)SHORT為扣除電阻 - 43 - Fig.3-2-4 Extrinsic Poly Gate電阻 - 45 - Fig.3-2-5 元件金屬接線電阻Rs、Rd,擴散層電阻R12 - 45 - Fig.3-2-6 Extrinsic 基板電容 - 46 - Fig.3-2-7 Intrinsic 寄生電容值 - 48 - Fig.3-2-8 使用RF量測萃取gm - 49 - Fig.3-2-9 Dual-Gate的Cgs2會比Cascode 來的小 - 50 - Fig.3-2-10 因為Dual-Gate的Cgs2比Cascode 小,所以可操作的頻寬會比較大……………………………………………………………… - 50 - Fig.3-2-11 使用2-port分析fT、fmax、K… - 51 - Fig.3-2-12 Dual-Gate因為OD面積小,所以在H21與fT會比Cascode好 - 52 - Fig.3-2-13 H21隨gm而改變 - 53 - Fig.3-2-14 fT將隨著gm而變化 - 53 - Fig.3-2-15 使用RF量測萃取gm,gm隨著偏壓而改變 - 54 - Fig.3-2-16 Vd=1V,Vg2=1.2V gm愈高Gain也跟著愈高 - 55 - Fig.3-2-17 K>1而 <1才會進入穩定狀態 - 57 - Fig.3-2-18 在偏壓改變之下S21愈小會有較好的K值 - 58 - Fig.3-2-19 Vd電壓從1V增加到2V,功率消耗增加二倍,但對gm提升並不大。………………………………………………………………..- 59 - Fig.3-2-20 Vd超過1V後,對H21與fT來看幾乎沒有太大的提升 - 59 - Fig.3-3-1 每一個Intrinsic電容隨的電壓改變的變化情形 - 62 - Fig.3-3-2 在固定Vg1=0.8V下,Vg2的變化對上fT的值 - 62 - Fig.3-3-3 將偏壓點操作在黑色陰影區會有較好的特性且有較低的功率消耗 - 63 - Fig.3-4-1 將萃取出的Model帶入ADS,與量測的資料做對照 - 64 - Fig.3-4-2 Dual-Gate模型萃取流程圖 - 65 - Fig.3-5-1 C2 Dual-Gate的Layout多了Metal 4,因此會與Gate的金屬走線Metal 2有重疊到 - 67 - Fig.3-5-2 Cgs2與Cgd1受Metal 4的關係,所以電容明顯有比C1 Dual-Gate來的要大 - 67 - Fig.3-5-3 在DC分析上的gm C2 Dual-Gate比C1 Dual-Gate大,而RF量測也一樣C2 Dual-Gate比較大一些 - 68 - Fig.3-5-4 因為gm比較大所以在H21上也會相對的來的高一些 - 68 - Fig.3-5-5 gm高伴隨著fmax也會有所增加 - 69 - Fig.3-5-6 穩定度與Gain較難同時被滿足,所以C2 Dual-Gate的K值穩定頻寬比C1 Dual-Gate的K值還小 - 69 - Fig.3-5-7 從低頻到高頻都小於1,滿足 要小於1才會穩定的條件 - 70 - Fig.3-5-8 (a)受到C2 Dual-Gate Guard ring距離比較遠的關係,所以Rsub電阻會比較大(b)距離遠電容會比較小 - 71 - Fig.3-5-9 C1 Dual-Gate比C2 Dual-Gate Re[Y22]還要高上許多 - 71 - Fig.3-5-10 S參數反應出C2 Dual-Gate與C1 Dual-Gate的S21與S22有明顯的不同 - 72 - Fig.3-5-11 因為OD面積比較小,所以C3 Dual-Gate的Cgs都比C1 Dual-Gate還小 - 73 - Fig.3-5-12 因為OD面積比較小,所以C3 Dual-Gate的Cgd都比C1 Dual-Gate還小 - 73 - Fig.3-5-13 C3 Dual-Gate的gm與C1 Dual-Gate差不多,但還是有略好一些 - 74 - Fig.3-5-14 面積小對fT整體來看是比較好的 - 74 - Fig.3-5-15 兩者的Gain與fmax差不多 - 75 - Fig.3-5-16 因為fmax差不多所以穩定度K值也沒有相差太大 - 75 - Fig.3-5-17 都有滿足 需小於1的條件 - 75 - Fig.3-5-19 (a)Fig.3-5-18 C3 Dual-Gate的面積比較小,所以在Rsub電阻也比C1 Dual-Gate還小 (b)面積小,所佔的電容比例也會比較小 - 76 -zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-3007200817412700en_US
dc.subject雙閘極zh_TW
dc.subjectDual-Gatelen_US
dc.subject疊接電晶體zh_TW
dc.subjectCascodeen_US
dc.title90奈米雙閘極疊接電晶體直流與射頻特性分析zh_TW
dc.titleCharacterization on DC and RF Performances of Dual-Gate Cascode Transistor in 90-nm CMOS Technologyen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
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