Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8423
標題: 應用於雙頻帶無線區域網路之射頻前端電路設計
The RF Front-End Design for Dual Band WLAN Applications.
作者: 詹爵安
Chan, Chueh-An
關鍵字: WLAN;無線區域網路;IEEE802.11a/b/g;dual band;LNA;Mixer;SSB Mixer;IEEE802.11a/b/g;雙頻帶;低雜訊放大器;混波器;單旁帶混波器
出版社: 電機工程學系所
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Soumyanath, “A 1.4V, 2.4/5 GHz, 90nm CMOS system in a package transceiver for next generation WLAN,” VLSI Circuits Digest of Technical Papers, pp. 294-297, June 2005. [5] Y. J. Ko, J. Y. Park, J. H. Ryu, K. H. Lee, and J. U. Bu, “A miniaturized LTCC multi-layered front-end module for dual band WLAN (802.1l a/b/g) applications,” Microwave Symposium Digest Pagers, pp. 563-566, 2004. [6] V. K. Dao, Q. D. Bui, and C. S. Park, “A multi-band 900MHz/1.8GHz/5.2 GHz LNA for reconfigurable radio,” RFIC Symposium, pp. 69-72, June 2007. [7] T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applications,” ISCAS, Vol. 1, pp. 217-220, May 2003. [8] V. K. Dao, B. G. Choi, and C. S. Park, “A dual-band CMOS RF front-end for 2.4/5.2 GHz applications,” Radio and Wireless Symposium, pp. 145-148, Jan. 2007. [9] L. H. Lu, H. H. Hsieh, and Y. S. Wang, “A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier,” Microwave and Wireless Components Letters, Vol. 15, pp. 685-687, Oct. 2005. [10] C. B. A. Edwin, S. I. Federico, and M. de la Rosa Jose, “Adaptive CMOS LNAs for beyond-3G RF receivers - a multi-standard GSM/WCDMA/BT/ WLAN case study,” ISCAS, pp. 417-420, May 2009. [11] G. Cusmai, M. Brandolini, P. Rossi, and F. Svelto, “A 0.18-μm CMOS selective receiver front-end for UWB applications,” IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1764-1771, Aug. 2006. [12] H. Hashemi and A. Hajimiri, “ Concurrent multiband low-noise amplifiers - Theory, design, and applications,” IEEE Transaction on Microwave Theory Technology, Vol. 50, No. 1, pp. 288-301, Jan. 2002. [13] M. B. Amor, A. Fakhfakh, H. Mnif, and M. Loulou, “ Dual band CMOS LNA design with current reuse topology,” Design and Test of Integrated Systems in Nanoscale Technology, 2006. [14] E. G. Ouail, K. Eric, J. B. Begueret, and B. Didier, “Concurrent dual-band low noise amplifier for 802.11a/g WLAN applications,” ICECS, pp. 66-69, Dec. 2006. [15] B. Razavi, RF Microelectronics, Prentice Hall Ptr, 1998. [16] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge Univ Pr, 2003. [17] B. Razavi, Design of analog CMOS integrated circuits. McGraw-Hill, Inc. International Edition, 2001. [18] T. P. Liu, “A 2.7V dual-frequency single-sideband mixer,” VLSI, pp. 124-127, 1998. [19] X. Jiang, W. Li, and N. Li, “QSSB mixer design for MB-OFDM UWB frequency synthesizer,” The 7th international conference on ASIC, pp. 688-691, Oct. 2007. [20] Jri Lee, “A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 3, pp. 566-573, Mar. 2006. [21] Leifso, C.; Nisbet, J, “A monolithic 6 GHz quadrature frequency doubler with adjustable phase offset,” IEEE Journal of Solid-State Circuits, Vol. 41, NO. 2, pp. 405-412, Feb. 2006. [22] A. A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE Journal of Solid-State Circuits, Vol. 30, pp. 1399-1410, Dec. 1995. [23] B. Razavi, RFIC Design Challenges, Design Automation Conference, 1998. [24] Guillermo Gonzlez, Microwave Transistor Amplifier Analysis and Design, New Jersey, Prentice Hall Inc, Second Edition, 1996. [25] D. K. Shaeffer, and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May 1997. [26] B. Gilbert, “A precise four quadrant multiplier with sub-nanosecond response,” IEEE Journal of Solid-State Circuits, Vol. SC-3, pp. 365-373, Dec. 1968. [27] Tai-You Lu and Wei-Zen Chen, “A 3-to-10GHz 14-band CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system,” IEEE ISSCC, pp. 126-127, Feb. 2008 [28] Chinmaya Mishra, Alberto Valdes-Garcia, Faramarz Bahmani, Anuj Batra, Edgar Sánchez-Sinencio, and Jose Silva-Martinez, “Frequency planning and synthesizer architectures for multiband OFDM UWB radios,” IEEE Transaction on Microwave Theory and Technology, Vol. 53, No. 12, pp. 3744-3755, Dec. 2005. [29] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE Journal of Solid-State Circuits, Vol. 39, pp. 1415-1424, 2004. [30] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi “CMOS mixers and polyphase filters for large rejection,” IEEE Journal of Solid-State Circuitss, Vol. 36, NO.6, pp. 873-887, Jan. 2001.
摘要: 
本論文主要研究應用於IEEE802.11a/b/g的無線區域網路雙頻接收機部份電路,內容包含前端電路基本原理、雙頻帶低雜訊放大器、直接降頻混波器以及單旁帶混波器等之設計。使用國家晶片系統設計中心(CIC)提供的TSMC0.35 m BiCMOS SiGe製程。本論文除了第二章講述電路基本概念外,將以三個電路的設計,分成三個章節來說明。
第三章的內容為設計採用雙頻帶輸出阻抗完成之雙頻帶低雜訊放大器。模擬結果增益大於7 dB,雜訊指數小於3.7 dB,輸入1dB壓縮點為–13 ~ – 4 dBm。量測結果顯示在2.4GHz以及5.2GHz,其增益分別為3.28dB以及–4.62dB,而雜訊指數為6.38 dB以及8.43 dB,功率消耗為22.44 mW。
第四章的設計則為直接降頻混波器,輸出零中頻的設計頻寬為5MHz,射頻操作在2.4GHz以及5.2GHz。模擬結果轉換增益大於10dB,雜訊指數小於15dB,輸入1dB壓縮點大於-20dBm。
第五章的設計為單旁帶混波器,利用上旁帶混波器以及下旁帶混波器的概念設計一個切換式的單旁帶混波器。此電路的輸出可以操作在2.4GHz以及5.2GHz,模擬結果輸出振幅大於300mVp,其附加之相位雜訊皆低於-120dBc/Hz@1MHz frequency offset。

This thesis studies mainly in dual band receiver for IEEE802.11a/b/g WLAN. The contents include fundamental principles of RF front-end, the low noise amplifier (LNA), the direct conversion mixer, and the single sideband mixer (SSBM). All of the designs use the TSMC 0.35 m BiCMOS SiGe process which is provided by the National Chip Implementation Center (CIC). Besides of the RF principles provided in chapter two, there are three additional chapters for three kinds of circuits in this thesis as described as followed.
In chapter three, we implemented the dual band LNA using the dual band resonance. The simulation results shows that the power gain is greater than 7dB, the Noise Figure (NF) is better than 3.7dB, and the input 1dB compression point is -13 to -4dBm for both bands. The measurement results shows that the power gain is 3.62dB and -4.62dB, SSB noise figure is 6.38dB and 8.43dB for 2.4GHz and 5.2GHz bands, respectively. The DC power consumption is 22.44mW.
In chapter four, we design a down conversion mixer, the output bandwidth is 5MHz, and the design is for 2.4GHz and 5.2GHz applications. The simulation results shows that the conversion gain is greater than 10dB, the SSB NF is smaller than 15dB, and the input 1dB compression point is greater than -20dBm.
In chapter five, we implemented a switching SSBM using upper sideband mixer and lower sideband mixer architecture. It is also for 2.4GHz and 5.2GHz applications. The simulation results show that the output swings is greater than 300mVp, and the phase noise is smaller than -120dBc/Hz at 1MHz offset frequency for both upper and lower sideband.
URI: http://hdl.handle.net/11455/8423
其他識別: U0005-0208200919492400
Appears in Collections:電機工程學系所

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