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A 8-bits successive approximation ADC
|關鍵字:||類比數位轉換器;adc||出版社:||電機工程學系所||引用:||S.-W. Lee, H.-J. Chung, and C.-H. Han, “C-2C digital-to-analogue converter on Insulator,” in Electron. Lett., pp. 1242- 1243, July 1999.  C. Lin, “ Pseudo C-2C ladder-based data converter technique,” in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48,pp. 927-929, Oct. 2001.  C.-S. Lin and B.-D. Liu, “A new successive approximation architecture for low-power low-cost CMOS A/D converter,” in IEEE International Solid-State Circuits Conference, Feb. 2003, pp. 54-62.  S. Mortezapour and E.K.F. Lee, “A 1-V, 8-bit successive approximation ADC in standard CMOS process,” in IEEE Journal of Solid-State Circuits, vol. 35, pp.642-646, Apr. 2000.  Park Jaejin, Park Ho-Jin, Kim Jae-Whui, Seo Sangnam, and P. Chung, “A 1 mW 10-bit 500KS/s SAR A/D converter,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 581-584, May 2000  C. J. B. Fayomi, G. W. Roberts, and M. Sawan, “A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18μm CMOS technology”, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 460-463, 2001.  J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-uW successive approximation ADC,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1261-1265, Jul 2003.  Y-M Liao and T-C Lee, “A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique,” IEEE VLSI-DAT, Apr. 2006  A. Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” IEE of Electronics Letters, vol. 32, Issue. 12,, Jun 1996  CMOS Analog Circuit Design by Phillip E. Allen, Douglas R. Holberg, and Allen (Jan 15, 2002)  Design of Analog CMOS Integrated Circuits by Behzad Razavi(Oct 1, 2003)||摘要:||
The demand of low power electronic device is become strong these years, especially in wireless and sensor network devices. Analog to digital converter (ADC) is the key building block of these devices. Therefore, a hot research topic is to reduce ADC power consumption. A main ADC architecture for low power system is charge redistribution successive approximation register (SAR).In this thesis,8bits sar adc is designed. The main research is sample and hold circuit, D/A convert ,digital control logic etc.
|Appears in Collections:||電機工程學系所|
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