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標題: 以電阻校正方法消除偏差電壓之六位元每秒四十億次取樣快閃式類比數位轉換器設計
A 4-GS/s 6-bits Flash ADC with Resistor-Regulator For Offset Cancellation
作者: 張軒瑜
Chang, Hsuan-Yu
關鍵字: 類比數位轉換器;ADC;快閃式;flash
出版社: 電機工程學系所
引用: M. Choi and A. A. Abidi, “A 6‐b 1.3‐Gsample/s A/D converter in 0.35μm CMOS,”IEEE J. Solid‐State Circuits, vol. 36, no. 12, pp.1847‐1858, Dec. 2001. [2] Iuri Megr and Declan Dalton, ”A 500-MSample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999. [3] Yuko Tamba and Kazuo Yamakido, ”A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 324-325, Feb. 2000. [4] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001. [5] X. Jiang and M.-C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuits,vol.40 , pp. 532–535, Feb.2005. [6] S. Park, Y. Palaskas, and M. P. Flynn, “A 4GS/s 4b flash ADC in 0.18μm CMOS,” IEEE J. Solid-State Circuits ,vol.42 , Sep.2007. [7] Ayman Ismail and Mohamed Elmasry , “A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC Converter in 0.13-μm CMOS Technology”, IEEE J. Solid-State Circuits ,vol.43 , Sep.2008. [8] Kazuaki Deguchi , Naoko Suwa , Masao Ito , Toshio Kumamoto , and Takahiro Miki ,“A 6-bit 3.5GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS” , IEEE J. Solid-State Circuits ,vol.43 , Oct.2008. [9] Chun-Ying , Michael Q. Le , and Kwang Young Kim , “A Low Power 6-bit Flash ADC With Rrference Voltage and Common-Mode Calibration” , IEEE J. Solid-State Circuits ,vol.44 , Apr.2009. [10] K. Uyttenhove and M. S. J. Steyaert, “A 1.8‐V 6‐Bit 1.3‐GHz flash ADC in 0.25‐um CMOS,” IEEE J. Solid‐State Circuits, vol. 38, no.7,pp.1115– 1122, July 2003. [11] Johnson Liu , “Mixed Signal IC Layout”, CIC , Workship on Fully Layout Technology . [12] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [13] O.Viitala, S.Lindfors and K.Halonen, “A 5-bit 1-GS/s Flash-ADC in 0.13-um CMOS Using Active Interpolation,”ISSCIR 2006 [14] J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert and G. Gielen, “A 8-bit 200 MS/s Interpolating/Averaging CMOS A/D Converter”, IEEE CICC, 2002. [15] Michael P. Flynn and David J. Allstot, ”CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol. 31, no.9, pp. 1248-1257, Sep. 1996. [16] C. Sandner et al., “A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-um Digital CMOS,”IEEE J. Solid-State Circuits, vol.40,pp.1499-1505, Jul. 2005. [17] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [18] Ying-Zu Lin; Cheng-Wu Lin; Soon-Jyh Chang;” A Digitally Calibrated 5-bit 3.2-GS/s Flash ADC ” in Proc. 2008 VLSI Design CAD Conference , August 2008. [19] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [20] S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18μm CMOS,” IEEE International Symposium on Circuits and Systems, May 2005. [21] B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, 1995. [22] 林凱琪,高速快閃式類比數位轉換器,台北科技大學電腦通訊與控制研究所碩 士學位論文,2002 [23] P. Scholtens and M. Vertregt, ”A 6b 1.6GSample/s flash ADC in 0.18μm CMOS using averaging termination,”IEEE Int.Solid‐State Circuits Conf, pp.168‐169, Feb 2002. [24] P. M. Figueiredo and J. C. Vital, “Termination of averaging networks in flash ADCs,”in Proc. 2004 Int. Symp. Circuits and Systs., vol. 1, May 2004, pp. 121–124. [25] H. Okada, Y. Hashimoto, K. Sakata, T. Tsukada, and K. Ishibashi, “Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um CMOS technology,” in Proc. ESSCIRC’03, Sep. 2003, pp. 711–714. [26] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [27] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001.
由於製程技術的進步,CMOS 積體電路的操作頻率也隨著增加。因此在類比與數位之間的介面也需要操作在極高的速度。高速類比數位轉換器被廣泛的應用在磁碟讀取通道、高速量測系統和超寬頻接收器的通訊系統中。
在此論文中,實現了一個取樣速率為每秒四十億次,六位元之快閃式類比數位轉換器。發生於類比數位轉換器前端之偏差電壓常導致輸出端的非線性誤差。因此我們應用了可修正偏差電壓的方法來改善此類比數位轉換器之效能。為了降低快閃式類比轉換器的輸入電容和偏差修正電路的數量,我們應用了主動式內插技術。模擬結果顯示此類比數位轉換器之信號-雜訊失真比(SNDR)在取樣速率4 GS/s,輸入訊號為76MHz時可達36.6dB,在輸入訊號為1GHz時可達到32dB。功率消耗在取樣頻率4 GS/s和1.2伏特電源供應時為308毫瓦。此晶片的面積為1.21- ,由TSMC 0.13-um 1P8M CMOS製程所製造。

Since the operating frequency of integrated circuits has been increasing due to the advance process technologies, thus the interfaces between the analog and the digital parts require to operate at ultra high speed. High-speed A/D converter are widely used for the applications in disk drive read channels, high-speed measurement systems, and communication systems such as UWB receivers.
In this thesis, a 4-GS/s 6-bits flash A/D converter is implemented. Because offset voltage in front-end of ADC usually results in nonlinearity in the outputs, an offset calibrating method is applied to improve the performance of the ADC. To reduce the input capacitance of the flash ADC and the amount of the calibration circuit, the active interpolation technique is adopted in this work. Simulation results show the ADC achieves a SNDR of 36.6 dB for a 76 MHz input at 4 GS/s, and 32 dB for a 1-GHz input. The power consumption is 308 mW at 4 GS/s from a 1.2-V supply. The chip occupies 1.21- active area, fabricated in TSMC 0.13-um 1P8M CMOS.
其他識別: U0005-1008200915072100
Appears in Collections:電機工程學系所

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