Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8458
DC FieldValueLanguage
dc.contributor盧志文zh_TW
dc.contributorChih-Wen Luen_US
dc.contributor許恆壽zh_TW
dc.contributorHeng-Shou Hsuen_US
dc.contributor.advisor楊清淵zh_TW
dc.contributor.advisorChing-Yuan Yangen_US
dc.contributor.author張軒瑜zh_TW
dc.contributor.authorChang, Hsuan-Yuen_US
dc.contributor.other中興大學zh_TW
dc.date2010zh_TW
dc.date.accessioned2014-06-06T06:41:36Z-
dc.date.available2014-06-06T06:41:36Z-
dc.identifierU0005-1008200915072100zh_TW
dc.identifier.citationM. Choi and A. A. Abidi, “A 6‐b 1.3‐Gsample/s A/D converter in 0.35μm CMOS,”IEEE J. Solid‐State Circuits, vol. 36, no. 12, pp.1847‐1858, Dec. 2001. [2] Iuri Megr and Declan Dalton, ”A 500-MSample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999. [3] Yuko Tamba and Kazuo Yamakido, ”A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 324-325, Feb. 2000. [4] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001. [5] X. Jiang and M.-C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuits,vol.40 , pp. 532–535, Feb.2005. [6] S. Park, Y. Palaskas, and M. P. Flynn, “A 4GS/s 4b flash ADC in 0.18μm CMOS,” IEEE J. Solid-State Circuits ,vol.42 , Sep.2007. [7] Ayman Ismail and Mohamed Elmasry , “A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC Converter in 0.13-μm CMOS Technology”, IEEE J. Solid-State Circuits ,vol.43 , Sep.2008. [8] Kazuaki Deguchi , Naoko Suwa , Masao Ito , Toshio Kumamoto , and Takahiro Miki ,“A 6-bit 3.5GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS” , IEEE J. Solid-State Circuits ,vol.43 , Oct.2008. [9] Chun-Ying , Michael Q. Le , and Kwang Young Kim , “A Low Power 6-bit Flash ADC With Rrference Voltage and Common-Mode Calibration” , IEEE J. Solid-State Circuits ,vol.44 , Apr.2009. [10] K. Uyttenhove and M. S. J. Steyaert, “A 1.8‐V 6‐Bit 1.3‐GHz flash ADC in 0.25‐um CMOS,” IEEE J. Solid‐State Circuits, vol. 38, no.7,pp.1115– 1122, July 2003. [11] Johnson Liu , “Mixed Signal IC Layout”, CIC , Workship on Fully Layout Technology . [12] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [13] O.Viitala, S.Lindfors and K.Halonen, “A 5-bit 1-GS/s Flash-ADC in 0.13-um CMOS Using Active Interpolation,”ISSCIR 2006 [14] J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert and G. Gielen, “A 8-bit 200 MS/s Interpolating/Averaging CMOS A/D Converter”, IEEE CICC, 2002. [15] Michael P. Flynn and David J. Allstot, ”CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol. 31, no.9, pp. 1248-1257, Sep. 1996. [16] C. Sandner et al., “A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-um Digital CMOS,”IEEE J. Solid-State Circuits, vol.40,pp.1499-1505, Jul. 2005. [17] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [18] Ying-Zu Lin; Cheng-Wu Lin; Soon-Jyh Chang;” A Digitally Calibrated 5-bit 3.2-GS/s Flash ADC ” in Proc. 2008 VLSI Design CAD Conference , August 2008. [19] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [20] S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18μm CMOS,” IEEE International Symposium on Circuits and Systems, May 2005. [21] B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, 1995. [22] 林凱琪,高速快閃式類比數位轉換器,台北科技大學電腦通訊與控制研究所碩 士學位論文,2002 [23] P. Scholtens and M. Vertregt, ”A 6b 1.6GSample/s flash ADC in 0.18μm CMOS using averaging termination,”IEEE Int.Solid‐State Circuits Conf, pp.168‐169, Feb 2002. [24] P. M. Figueiredo and J. C. Vital, “Termination of averaging networks in flash ADCs,”in Proc. 2004 Int. Symp. Circuits and Systs., vol. 1, May 2004, pp. 121–124. [25] H. Okada, Y. Hashimoto, K. Sakata, T. Tsukada, and K. Ishibashi, “Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um CMOS technology,” in Proc. ESSCIRC’03, Sep. 2003, pp. 711–714. [26] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [27] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001.zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/8458-
dc.description.abstract由於製程技術的進步,CMOS 積體電路的操作頻率也隨著增加。因此在類比與數位之間的介面也需要操作在極高的速度。高速類比數位轉換器被廣泛的應用在磁碟讀取通道、高速量測系統和超寬頻接收器的通訊系統中。 在此論文中,實現了一個取樣速率為每秒四十億次,六位元之快閃式類比數位轉換器。發生於類比數位轉換器前端之偏差電壓常導致輸出端的非線性誤差。因此我們應用了可修正偏差電壓的方法來改善此類比數位轉換器之效能。為了降低快閃式類比轉換器的輸入電容和偏差修正電路的數量,我們應用了主動式內插技術。模擬結果顯示此類比數位轉換器之信號-雜訊失真比(SNDR)在取樣速率4 GS/s,輸入訊號為76MHz時可達36.6dB,在輸入訊號為1GHz時可達到32dB。功率消耗在取樣頻率4 GS/s和1.2伏特電源供應時為308毫瓦。此晶片的面積為1.21- ,由TSMC 0.13-um 1P8M CMOS製程所製造。zh_TW
dc.description.abstractSince the operating frequency of integrated circuits has been increasing due to the advance process technologies, thus the interfaces between the analog and the digital parts require to operate at ultra high speed. High-speed A/D converter are widely used for the applications in disk drive read channels, high-speed measurement systems, and communication systems such as UWB receivers. In this thesis, a 4-GS/s 6-bits flash A/D converter is implemented. Because offset voltage in front-end of ADC usually results in nonlinearity in the outputs, an offset calibrating method is applied to improve the performance of the ADC. To reduce the input capacitance of the flash ADC and the amount of the calibration circuit, the active interpolation technique is adopted in this work. Simulation results show the ADC achieves a SNDR of 36.6 dB for a 76 MHz input at 4 GS/s, and 32 dB for a 1-GHz input. The power consumption is 308 mW at 4 GS/s from a 1.2-V supply. The chip occupies 1.21- active area, fabricated in TSMC 0.13-um 1P8M CMOS.en_US
dc.description.tableofcontents目錄 誌謝 摘要(中文) - - - - - - - - - - - - - - - - - - - - i 摘要(英文) - - - - - - - - - - - - - - - - - - - - -ii 目錄 - - - - - - - - - - - - - - - - - - - - - - iii 第一章 緒論 1.1研究動機 1 1.2內容編排 3 第二章 類比數位轉換器簡介 2.1 類比數位轉換器資料轉換理論及重要參數介紹 2.1.1 解析度 4 2.1.2 量化誤差(Quantization Noise) 5 2.1.3 取樣定理 6 2.1.4 靜態特性 7 2.1.5 動態範圍(Dynamic Range) 8 2.1.6 無雜散動態範圍(Spurious Free Dynamic Range) 9 2.2 快閃式類比數位轉換器(Flash Analog-to-digital Converter) 10 2.3 近幾年高速類比數位轉換器的架構(參考paper) 2.3.1 A 1-GHz Signal Bandwidth 6-bit CMOS ADC With Power-Efficient Averaging 11 2.3.2 A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS 12 2.3.3 A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC Converter in 0.13-μm CMOS Technology 13 2.3.4 A 6-bit 3.5GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS 14 2.3.5 A Low Power 6-bit Flash ADC With Rrference Voltage and Common-Mode Calibration 16 第三章 4GS/s-6位元快閃式類比數位轉換器之設計及考量 3.1 分壓電阻參考電壓產生器 19 3.1.1 饋通效應 20 3.1.2 分壓電阻串之單位電阻不匹配 23 3.2 前置放大 26 3.2.1 第一級前置放大器 26 3.2.2 前三級放大器 28 3.2.3 比較器(comparator) 29 3.3 前置放大器加比較器模擬 30 3.4 主動式內插 32 3.5 偏差電壓校正 34 3.5.1 校正機制 34 3.5.2 電阻校正器 35 3.5.3 ΔR 的設計考量與校正範圍 37 3.5.4 校正方法 37 3.6 降頻電路 38 3.7 時脈緩衝器 39 3.8 編碼電路 40 3.8.1 泡沫錯誤(Bubble Error) 41 3.8.2 溫度碼 第四章 類比數位轉換器模擬、佈局 4.1 電路佈局圖 48 4.2 模擬結果 49 4.2.1 無誤差之模擬 49 4.2.2 加上額外誤差之模擬 51 4.3 預計效能與比較表 54 第五章 晶片量測結果 5.1 量測環境 56 5.2 量測結果 65 參考文獻 67 附錄zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1008200915072100en_US
dc.subject類比數位轉換器zh_TW
dc.subjectADCen_US
dc.subject快閃式zh_TW
dc.subjectflashen_US
dc.title以電阻校正方法消除偏差電壓之六位元每秒四十億次取樣快閃式類比數位轉換器設計zh_TW
dc.titleA 4-GS/s 6-bits Flash ADC with Resistor-Regulator For Offset Cancellationen_US
dc.typeThesis and Dissertationzh_TW
item.grantfulltextnone-
item.openairetypeThesis and Dissertation-
item.languageiso639-1en_US-
item.fulltextno fulltext-
item.cerifentitytypePublications-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
Appears in Collections:電機工程學系所
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