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dc.creatorChia-Feng Juangen_US
dc.creatorKai-Jie Juangen_US
dc.description.abstractThis paper proposes a reduced interval type-2neural fuzzy system using weighted bound-set boundaries(RIT2NFS-WB) for the simplification of type-reduction operations.The objective of this simplification is to reduce the systemtraining time in software implementation and chip size inhardware implementation, especially when the number of rulesis large. The antecedent part in the RIT2NFS-WB uses intervaltype-2 fuzzy sets (IT2FSs), and the consequent part can be of theTakagi–Sugeno–Kang (TSK) or Mamdani type.The RIT2NFS-WBis built through an online structure and parameter learningto improve model accuracy. In addition, the interpretability ofthe RIT2NFS-WB is improved by considering distributions ofthe IT2FSs in input variables. A distinguishability-oriented costfunction is used in parameter learning to generate distinguishableIT2FSs and improve semantics-based interpretability. Forhighly overlapped IT2FSs, they are merged to reduce the numberof IT2FSs and improve complexity-based interpretability.The software-implemented TSK-type RIT2NFS-WB is hardwareimplementedon a field-programmable gate array chip. To acceleratethe chip execution speed, the chip utilizes not only the parallelexecution properties of fuzzy rules and bound-set boundaries butthe pipeline technique as well. In particular, the flexibility of thechip is considered so that no redesign of the circuits is requiredwhen the RIT2NFS-WB is applied to different problems. The characteristicsof the software- and hardware-implemented RIT2NFSWBare verified through various examples and comparisons withvarious type-1 and interval type-2 fuzzy models.en_US
dc.relationIEEE TRANSACTIONS ON FUZZY SYSTEMS, Volume 21, Issue 3.en_US
dc.subjectDistinguishable fuzzy sets, interpretable fuzzysystemsen_US
dc.subjectneural fuzzy systems (NFSs)en_US
dc.subjecttype-2 fuzzy chipsen_US
dc.subjecttype-2fuzzy systemsen_US
dc.subjecttype reductionen_US
dc.titleReduced Interval Type-2 Neural Fuzzy System UsingWeighted Bound-Set Boundary Operation forComputation Speedup and Chip Implementationen_US
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