Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8493
標題: 本地振盪信號源產生電路設計
Local Oscillation Signal Source Generation Circuit Design
作者: 吳明峰
Wu, Ming-Fong
關鍵字: Current reuse;電流在利用;frequency divider;injection locked;quadrature signal;除頻器;注入鎖定;四相位信號
出版社: 電機工程學系所
引用: [ 1 ] 王詮慶, ”應用於MB-OFDM Mode-1 UWB 接收機之CMOS 壓控振盪器與頻率合成器的研制”,國立成功大學電腦與通訊工程研究所碩士論文,pp.1-22,2007年七月. [ 2 ] Thomas H. Lee.,”The Design of CMOS Radio-Frequency Integrated Circuits”,Ne- New York Cambridge University Press, 1998. [ 3 ] Donhee Ham,and Ali Hajimiri,"Concepts and Methods in Optimization of Integrated LCVCOs", IEEE Journal Of Solid-State Circuits, VOL. 36, NO. 6, JUNE 2001. [ 4 ] Leeson, D. B.,"A Simple Model of FeedbackOscillatorNoiseSpectrum" ,Proc.IEEE, 54, pp. 329–330,February 1966 [ 5 ] Behzad Razavi ,"RF Microelectronics” , Prentice-Hall, 1998. [ 6 ] RANEYURI KURORAWA,”Some basic characteristics of broadband Negative Rsistance Oscill-ator Circuit”,Bell System Technical Journal, ,Vol.48, pp.1937-1955,July 1969 [ 7 ] Stadius,K.Kaunisto,R.Porra,V. ,"Monolithic tunable capaci- tors for RF applications”,IEEE ISCAS ,Vol.1, pp.488-491 May 2001 [ 8 ] Behazd Razavi,”Design of Anglog CMOS Intergrated Circuits”,pp.78-5052006年6月 [ 9 ] Kari Staditis, Risto Kaunisto and Veikko Porra,"Monolithic tunable capaci- tors for RF applications”,IEEE International Symposium on Circuits and systems ,Vol.1, pp.488-491, May 2001 [10] 高曜煌,”射頻鎖相迴路IC設計,”滄海書局,pp.75,October 2005。 [11] Ahmadreza Rofougaran, Jacob Rael, Maryam Rofougaran, Asad Abidi,” A 900 MHz CMOS LC-oscillator with quadrature outputs”, IEEE Int Solid-State Circuits C-onf. ,pp.392- 393,Feb 1996 [12] Rofougaran,A.Rael,J.Rofougaran,M.Abidi, A.,” A 900 MHz CMOS LC-oscillator with quadrature outputs”,IEEE Int Solid-State Circuits C-onf ,pp.392- 393,Feb 1996 [13] Marc Tiebout,“Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,”IEEE Journal of Solid-State Circuits, vol.36, pp1018-1024, July 2001 [14] Jong-Phil Hong, Seok-Ju Yun, Nam-Jin Oh, and Sang-Gug Lee, “A 2.2-mW Backgate Coupled LC Quadrature VCO With Current Reused Structure,” IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 4, APRIL 2007 [15] Hye-Ryoung Kim, Choong-Yul Cha, Seung-Min Oh, Moon-Su Yang, and Sang-Gug Lee “A very low-power quadrature VCO with back-gate coupling, ''IEEE Journal Of Solid-State Circuits, vol. 39, no. 6, pp. 952–955, Jun. 2004 [16] Xiaoyong Li,, Sudip Shekhar, and David J. Allstot, “Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18- um2 CMOS,” IEEE Journal Of Solid-State Circuits vol. 40, no. 12, pp. 2609–2619, Dec. 2005 [17] DIJKMANS Carel, THOMPSON Michael, “A 0.18 um CMOS 2.45 GHz low-power quadratureVCO with 15% tuning range,” Radio frequency integrated circuits symposium , pp. 67–70, Jun. 2002. [18] Ahmadreza Rofougaran , Glenn Chang , Jacob J. Rael, James Y.-C. Chang , Maryam Rofougaran , Paul J. Chang , Masoud Djafari , Edward W. Roth , Asad A. Abidi , Henry Samueli ,“A single-chip 900-MHz spread spread -spectrum wireless transceiver in 1- μm CMOS—Part I: Architecture and transmitter design,”IEEE Journal of Solid-State Circuits, vol. 33, pp. 515, Apr. 1998 [19] Sheng-Che TSENG, Chinchun MENG and Wei-Yu CHEN, “True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalar,” Inst Electron Inf Commun eng Transactions on Electronics, Vol. E89-C, No. 6, June 2006. [20] j p silver,”Gilbert Cell Mixer Design Tutorial“ [21] Ravender Goyal, John Wiley,”high-frequency Anglog Integrated-circuit Design”,New York, 1995 [22] CHIU WEI-YU, HUANG FAN-HSIU, WU YEN-SHIAN, LIN DON-MIN, CHAN YI-JEN, CHEN SHU-HAN, CHYI JEN-INN, SHI JIN-WEI, “ Improvement of mesa-sidewall leakage current using BCB sidewall process in InGaAs/InP MSM photodetector,”Japanese Journal of Application physic s, vol. 44, no.4B, pp.2586-2587, 2005 s, vol. 44, no.4B, pp.2586-2587, 2005 [23] RANEYURI KURORAWA, “Injection locking of microwave solid-state oscillators", Proc. IEEE,vol. 61, pp.1336-1410, Oct. 1973. [24] Hui Wu, Lin Zhang, “A 16-to-18GHz 0.18mm Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider,” IEEE International Solid-State Circuits Conference. Digest Of Twchnical Papers, pp. 27-29, Feb., 2006 [25] Hui Wu and Ali Hajimiri, “A 19GHz, 0.5mW, 0.35mm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement,” IEEE Interna- tional Solid-State Circuits Conference. Digest Of Twchnical Papers, pp. 412-413, Feb., 2001. [26] Roberto Aparicio and Ali Hajimiri, "A noise-shifting differential Colpitts VCO,"IEEE Solide-State Circuits Circuits,pp 1728-1736,Dec. 2002 [27] Hsinchu, "study on High Speed Ring Oscillators in Transmitter Chip for Wireless Communication," Communication Engineering,2003 [28] Lacaita, A.L. and Samori, C. "Circuits and Systems II: Analog and Digital Signal Processing," IEEE Transactions on see also Circuits and Systems II, 1998 [29] Ken Yamamoto, Takayasu Norimatsu and Minoru Fujishima,”High-speed and wide-tuning-range LC frequency divider,” IEEE International Symposium on Circuits and sys-tems,pp.361-364,2004 [30] Chien-Feng Lee Sheng- Lyang Jang, ,“A Wide Locking Range Differential CoLpitts Injection Locked Frequency Divider”, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS,VOL. 17, NO. 11, NOVENBER 2007. [31] 洪英真,”適用於GHz 頻段頻率合成器之CMOS 電路技術”,國立中央大學電機工程程研究所碩士論文,pp.1-21,2001年七月 [32] 郭文福,”應用於超寬頻無線網路之壓控振盪器設計”,國立中興大學電機工程程研究所碩士論文,pp.1-64,2008年七月
摘要: 
本論文以實現本地振盪信號源產生電路設計為主要出發點,探究相關電路設計上的問題並實際製作出電路。我們使用的是TSMC 0.18μm 1P6M RFCMOS 1.8V供應電壓製程,設計出四個不同的電路:包括了壓控振盪器及除頻器。故整體將以這些電路為主要架構,分成四個主要章節來講述其電路原理、模擬結果和部份成功下線晶片最後的量測結果。

第二章的內容主要在設計一個LC共振腔結合背閘極耦合之電流再利用式互補式交叉耦合對正交四相位壓控振盪器。電路設計概念上主要利用兩個技巧:第一是利用電流再使用,以使功率消耗變小;第二個則是背閘極耦合,它會使電路的Phase noise變好,也有進一步降低功耗的作用。所設計出的電路,模擬結果可調頻寬範圍在3.6GHz到4.4GHz間,中心頻率4GHz處的相位雜訊模擬值可達-120dBc/Hz@1MHz frequency offset。

第三章的內容則在設計一個注入鎖定式四相位除三電路,主要為因應國科會計畫所需而做的研究。我們完成了一個3.6GHz~3.9GHz的除三電路,其架構中使用了注入鎖定除二電路,再使用回授技巧與輸入訊號在mixer混頻,並將混頻輸出電流注入前述除二電路來完成此架構。此電路成功在國家晶片中心下線,量測到功率消耗為21.6mW,量測顯示除三範圍在3.51GHz~3.79GHz,相位雜訊都優於-124.41dBz/Hz@1MHz frequency offset。

第四章的設計則為整合壓控振盪器與除三電路:其中壓控振盪器是採用NMOS對和PMOS對之LC tank壓控振盪器,由於上升時間和下降時間對稱,可減少1/f 雜訊,設計出之可調振盪頻率在6GHz~7.5GHz;除頻器則是採用第三章之電路架構並進行修改,使這除頻器的消耗功率更低,約2.934mA。利用這兩個電路來整合,並成功在國家晶片中心下線,此電路已進行量測並觀察其效能如何,也發現若干待改進處。

第五章的設計則為寬頻注入鎖定的差動考畢子除頻器,是採用考畢子震盪器和電壓注入方式設計而成的除二電路,並和電流注入是比較其優缺點。達成之電路的注入鎖定範圍是8.53GHz~11.88GHz;量測上輸入和輸出都採打磅線方式,並採用FR4板量測,並觀察其效能如何。

In this thesis, we study a new architecture to realize the local oscillation signal source generation, including related circuits design, chip tape-out, measurement and trouble shooting. We have designed four different circuits using the TSMC 0.18μm 1P6M RFCMOS 1.8V process, including the voltage control oscillators and the frequency dividers. The contents of this thesis can be divided into four main chapters as described following, including circuit design concept, simulation results, and final measurement of some chips for every circuit.
In Chapter 2, a LC tank based back-gate coupling current-reused complementary cross-coupled quadrature voltage control oscillator is presented. It uses two important techniques: first, the current-reused architecture is adopted to decrease the power consumption; and second, the back-gate coupling technique makes the phase noise of circuit better and can further decrease the power consumption. The simulation results show that the tuning range is 3.6GHz~4.4GHz, and the phase noise is -120dBc/Hz@1MHz frequency offset when the oscillator is operated at center frequency, 4GHz.
In Chapter 3, we design a new type of divide-by-3 injection-locked frequency divider with quadrature outputs, which is one part of our project supported by the National Science Council. A 3.6GHz~3.9GHz divide-by-3 frequency divider is presented, in which, we use divide-by-2 injection-locked frequency dividers and use feedback technique to mix with the input signal to generate the division ratio. This chip is successfully taped out through the National Chip Implementation Center and the DC power consumption of it is 21.6mW. The operation frequency of this divide-by-3 frequency divider ranges from 3.51GHz to 3.79GHz. The phase noise is lower than -124.41dBz/Hz @1MHz frequency offset.
In Chapter 4, the integration of the voltage control oscillator and the divide-by-3 frequency divider is demonstrated. In our design, the voltage control oscillator uses NMOS pairs and PMOS pairs to form a LC tank based VCO. Because the rising time and the falling time of the output waveform is designed to be symmetrical, it can reduce the 1/f noise. The tuning range is between 6GHz~7.5GHz. The frequency divider adopts the similar design as that presented in Chapter 3, and it is revised to be with lower power consumption, that is, about 2.934mW. By integrating these two circuits, a LO generation circuit is taped out through the National Chip Implementation Center and the measurement is also performed to observe its performance. Some problems are investigated for future improvement of this design.
The design presented in Chapter 5 is a wide locking range differential Colpitts injection-locked frequency divider. It uses Colpitts oscillator as the basic structure and adopt voltage-injection to form a divide-by-2 frequency divider, and we also compare its performance with that by current-injection. The locking range of the resulting circuit is between 8.53GHz~11.88GHz. The measurements are performed on the FR4 PCB with bounded wires for both inputs and outputs, and observe the resultant performances.
URI: http://hdl.handle.net/11455/8493
其他識別: U0005-1407200916213500
Appears in Collections:電機工程學系所

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