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Design of Switched-Capacitor Voltage Reference and PMOS Charge Pump Circuits
|關鍵字:||Voltage reference;參考電壓;Switched-capacitor;Charge pump;切換式電容;電荷幫浦||出版社:||電機工程學系所||引用:|| 李俊欣, “改良式二相位和四相位電荷幫浦及電壓調節器設計,” 2007年碩士論文, 國立中興大學  陳志興, “低功率嵌入式非揮發性記憶體系統及控制信號產生,” 2006年碩士論文, 國立中興大學  B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.  David A. Johns and Ken Martin, Analog Integrated Circuit Design, New York: Wiley, 1997.  J. Dickson, “On-Chip High-Voltage Generation NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 374-378, Mar. 1976.  G. De Vita and G. Iannaccone, “A Sub-1-V, 10ppm/°C, Nanopower Voltage Reference Generator,” IEEE J. Solid-State Circuits, vol. 42, pp. 1526-1542, no. 7, July, 2007.  K. N. Leung and P. K. T. Mok, “A CMOS Voltage Reference Based on Weighted ΔVGS for CMOS Low-Dropout Linear Regulators,” IEEE J. Solid-State Circuits, vol. 38, pp. 146-150, no. 1, Jan. 2003.  L. H. De Carvalho Ferreira and T. C. Pimenta, “A CMOS Voltage Reference for Ultra Low-Voltage Applications,” IEEE International Conference on Electronics Circuits and Systems, pp. 1-4, Dec. 2005.  H.-W. Huang, C.-Y. Hsieh, K.-H. Chen, and S.-Y. Kuo, “A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference,” IEEE International Solid-State Circuits Conference, pp. 438-626, Feb. 2008.  A. Cabrini A. Fantini and G. Torelli, “High-Efficiency Regulated Charge Pump for Non-Volatile Memories,” IEEE International Conference on Electronics Circuits and Systems, pp. 720–723, 2006.  B. R. Gregoire, “A Compact Switched-Capacitor Regulated Charge Pump Power Supply,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1944-1953, August 2006.  J. Soldera, A. Vilas Boas, and A. Olmos, “A Low Ripple Fully Integrated Charge Pump Regulator,” Proceedings of the 16th Conference on Integrated Circuits and Systems Design, SBCCI 2003, pp. 177-180, 2003.  A. Saiz-Vela, P. Miribel-Català, M. Puig-Vidal, and J. Samitier, “An Electron Mobility Independent Pulse Skipping Regulator for a Programmable CMOS Charge Pump,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 117-120, May 2005.  C.-Y. Hsieh, P.-C. Fan, and K.-H. Chen, “A Dual Phase Charge Pump with Compact Size,” IEEE International Conference on Electronics Circuits and Systems, pp. 202-205, Dec. 2007.  Umberto Gatti, Franco Maloberti, and Guido Torelli, “A Novel CMOS Linear Transconductance Cell for Continuous-Time Filters,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1173-1176, May 1990.  Libin Yao, Michiel Steyaert, and Willy Sansen, “A 0.8-V, 8-μW, CMOS OTA with 50-dB Gain and 1.2-MHz GBW in 18-pF Load,” European Solid-State Circuits Conference, pp.297-300, Sept. 2003.  Airong Liu and Huazhong Yang, “Low Voltage Low Power Class-AB OTA with Negative Resistance Load,” International Conference on Communications Circuits and Systems, pp. 2251-2254, June 2006.  S. Szczepanski, J. Jakusz, and R. Schaumann, “A linear fully balanced CMOS OTA for VHF filterfing Applications,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Proc., vol. 44 pp. 174-187, Mar. 1997.  Po-Hsuan Huang, Hongchin Lin, and Yen-Tai Lin, “A Simple Subthreshold CMOS Voltage Reference Circuit with Channel Length Modulation Compensation,” IEEE Trans. Circuits and Systems II, vol. 53, no. 9, pp. 882-885, 2006.  R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd Ed., Kluwer Academic Publishers, 2001.  J. Falin and L. Pham, “Tips for Successful Power-up of Today’s High-Performance FPGAS,” Texas Instrument Analog Applications.  X. Liu, S. Guo, S. Wang, F. Xu, G. Du, and Y. Chang, “Analysis and Design of a High Efficiency Boost DC-DC Converter Based on Pulse-Frequency Modulation,” IEEE International Symposium on Integrated Circuits, pp. 26-28, Sept. 2007.  J. Pan and T. Yoshihara, “A Charge Pump Circuit without Overstress in Low-Voltage CMOS Standard Process,” IEEE Conference on Electron Devices and Solid-State Circuits, pp. 501-504, 2007.  M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Design of Charge Pump Circuit with Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes,” IEEE J. Solid-State Circuits, vol. 41, pp. 1100-1107, no. 5, May 2006.  P. Favrat, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, pp. 410-416, March. 1998.  J. Wu and K. Chang, “MOS charge pumps for low-voltage operation,” IEEE J. Solid-State Circuits, vol. 33, pp.592-597, April. 1998.  G. Palumbo, D. Pappalardo, and M. Gaibotti, “Charge-pump circuits: power-consumption optimization,” IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, pp. 1535 – 1542, Nov. 2002  E. Racapé, and J.-M. Daga “A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process,” Proc. of IEEE European Conf. on Solid-State Circuits, pp. 77-80, Sept. 2005.  K. Ohsaki and N. Asamoto, “A Planar Type EEPROM cell Structure by Standard CMOS Process and Applications” IEEE VLSI Tech. Symp., pp. 55-56, 1993.  A. O. Adan, R. Smolen, N. Tokuyama, T. Ohmi, P. Wright, R. Madurawe, A. Kagisawa, and F. Gregoire, “A scaled 0.6um high high speed PLD technology using single-poly EEPROM’s” IEEE Custom Integrated Circuits Conference, pp. 55-58, 1995.  M.-H. Chi and A. Bergemont, “A New Single-poly Flash Memory Cell with Low-voltage and Low-power Operations for Embedded Applications” IEEE Device Research Conference, pp. 126-127, 1997.  Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications,” VLSI Tech. Symposium, 2003.||摘要:||
在電荷幫浦電路中，我們提出了一個2倍壓的時脈產生電路來控制開關電晶體的閘極，以改善Racapé電荷幫浦中開關電晶體的壓差過低的缺點，如此可以使得操作在低供應電壓和較高負載電流下的Racapé電荷幫浦也有很高的輸出電壓。我們採用TSMC 0.18μm製程來驗証我們所提出的電路架構，當操作在1.8V的電源電壓且無負載下，兩級的改良式Racapé電荷幫浦電路，其量測的輸出電壓可高達5.16 V。
Much higher than supply voltages are required for program and erase of non-volatile memories, high voltage regulator circuits are usually used to have a stable high voltage. For embedded non-volatile memories, the regulator requires a stable reference voltage circuit and a charge pump to generate a voltage higher than supply voltage. The challenge is both of them have to be designed using the standard CMOS technology for the embedded system. This thesis is focused on two circuit blocks. The first block is to modify driving capability of Racapé's charge pump circuit. The second one is to design a voltage reference using switched-capacitor approach.
A simple two-phase clock scheme to enhance the driving capability of Racapé's charge pump circuit for low-voltage applications is proposed in this thesis. The proposed PMOS charge pump was simulated and verified by using TSMC 0.18μm CMOS technology. The measured results show that, under no load current, the output voltage of the proposed charge pump is about 5.16V at a supply voltage of 1.8V and a frequency of 10MHz.
A switched-capacitor voltage reference circuit that controlled by two out-of-phase clocks is presented. The proposed reference circuit can generate a voltage using a sub-threshold diode-connected NMOS transistor that is switched between two different bias conditions. The main features of the proposed reference circuit include generating a sub-1V voltage reference, no parasitic BJT devices, small chip area, and operated at low supply voltage.
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