Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8523
標題: 應用於嵌入式系統晶片支援多層級通訊協定之矽智產介面自動合成產生器
Automatic IP Interface Synthesis Supporting Multi-Layer Communication Protocols in SoC Designs
作者: 羅華信
Luo, Hua-Hsin
關鍵字: intellectual property;矽智產;interface synthesis;multi-layer communication;signal mapping;timing adjustment;介面合成;多層級溝通;信號對應;時序調整
出版社: 電機工程學系所
引用: [1]A. Rajawat, M. Balakrishnan, and A. Kumar, “Interface synthesis : issues and approaches”, in Proc. IEEE Int. Conf. on VLSI Design, 2000, pp. 92-97. [2]J. Smith, and G.D. Micheli, “Automated composition of hardware components”, in Proc. of 35th DAC, 1998, pp. 14-19. [3]R. Passerone, J.A. Rowson, and A. Sangiovanni-Vincentelli, “Automatic synthesis of interfaces between incompatible protocols”, 35th DAC, 1998, pp. 8-13. [4]V. D'Silva, S. Ramesh, and A. Sowmya, “Bridge over troubled wrappers: Automated interface synthesis” 17th Int. Conf. on VLSI design, 2004, pp. 189-194. [5]V. Androutsopoulos and others “Protocol converter synthesis”, Computers and Digital Techniques, in Proc. IEE. vol. 151, no. 6, 2004, pp. 391-401. [6]H. Cho, S. Abdi, and D. Gajski, “Interface synthesis for heterogeneous multi-core systems from transaction level models”, in Proc. LCTES Conf. ACM SIGPLAN Notices, 2007, pp. 140-142. [7]J.-M. Daveau, G.F. Marchioro, T. Ben-Ismail, and A.A. Jerraya, “Protocol selection and interface generation for hw-sw codesign” IEEE Trans. on VLSI Systems, 1997, pp. 136-144. [8]S. Watanabe and others, “Protocol Transducer Synthesis using Divide and Conquer approach”, in Proc. of 12th ASP-DAC, 2007, pp. 280-285. [9]C.R. Yun and others, “Automatic interface synthesis based on the classification of interface protocols of IPs ”, in Proc. of ASP-DAC, 2008, pp.589-594. [10]B.-I. Park, I.-C. Park, and C.-M. Kyung, “Interface synthesis for IP based design”, in Proc. of 2th AP-ASIC, 2000, pp. 227-230. [11]A. Gerstlauer, R. Dongwan Shin Domer, and D.D. Gajski, “System-level communication modeling for network-on-chip synthesis”, in Proc. of the ASP-DAC, vol. 1, 2005, pp. 45-48. [12]A. Gerstlauer and others, “Automatic Layer-Based Generation of System-On-Chip Bus Communication Models”, IEEE Tran. On CAD of Integrated Circuits and Systems, vol. 26, no 9, 2007, pp. 1676-168. [13]Y.T. Hwang and S.C. Lin, ”Automatic Protocol Translation and Template Based Interface Synthesis for IP Reuse in SOC”, IEEE Conf. On Circuit and System, vol. 1, 2004, pp. 565-568. [14]“AMBATM Specification”, Rev. 2.0, May 13, 1999. [15]“VSI AllianceTM Virtual Component Interface Standard”, Rev. OCB 2 2.0, Aug 24, 2000. [16]“Specification for the WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores”, Rev. B.3, Sept 7, 2002. [17]“PCI Local Bus Specification” Rev. 2.3, Oct 31, 2001. [18]“Open Core Protocol Specification” Rev. 2.1, 2005. [19]Clifford E. Cummings, 2002, “Simulation and Synthesis Techniques for Asynchronous FIFO Design”, Sunburst Design, March. [20]DCT in XviD. Summarized by: Andrej Rikovsky. [21]Socle CDK Connectivity Specification. [22]Micbael Barr, Antbony Massa, “Programming Embedded Systems with C and GNU Development Tools”, 2nd edition, O'Reilly, Oct. 2006. [23]Jonathan Corbet, Alessandro Rubini & Greg Kroah-Hartman, “Linux Device Drivers”, 3rd edition, O'Reilly, Feb. 2005. [24]CICeNews : http://www.narl.org.tw. [25]Linux Kernel Documentation : http://www.mjmwired.net.
摘要: 
在系統單晶片(System on a Chip,以下簡稱SoC)設計如今都以矽智產(Silicon Intellectual Property,簡稱IP)為基礎的方式做設計來縮短系統開發時程,而系統在整合上所遭遇到挑戰便是各種異質介面之間的IP整合,IP間通常擁有各種不同溝通介面以處理系統協定間互相連結轉換,諸如額外的轉接器或是IP包裹器的設計,而良好的介面設計是系統整合成功的關鍵,然而介面的設計通常需針對其專屬需求設計且是冗雜且易錯的工作。
在本論文中,我們提出介面設計自動化的方法,有效降低SoC系統IP整合所需耗費的心力,縮短SoC系統開發時程,其導入了多層級溝通協定的概念在合成處理上,使介面自動產生上介面設計者能針對我們所定義不同層級選擇對應的介面電路功能決定電路複雜度,首先我們將開發一多層級介面電路架構模板,其設計上包含介面電路協定定義規範、信號對應與時序調整方式、介面電路架構對應方式,我們利用各種不同電路系統以及各種不同匯流排協定做為實例,產生不同合成選擇之介面電路,此外為了顯示我們所設計自動產生器可以縮短系統設計週期,在實驗數據方面透過比較人工設計版本介面電路與自動化產生版本介面電路之差異性。

System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP integration is one of the most challenging works in SoC designs. Because IP blocks often have different communication interface to cope with the protocol of the interconnect structure, extra adaptor circuit or bus wrapper must be provided to IPs. This is also known as the interface synthesis problem. In the past, IP interface designs were mostly tackled in an ad-hoc manner, which was tedious and error prone.
In this thesis, we present an automatic interface synthesis system to expedite the IP integration process in SoC designs. The concept of multi-layer communication protocols is incorporated into the synthesis process so that interface design targeting different levels of functionality and circuit complexity can be generated automatically. The multi-layered interface architecture template designs are developed in the first place. We then outline the methodology of interface synthesis, which includes protocol specifications, signal mapping & timing adjustment, and architecture mapping. Interface designs for several benchmark systems are developed using different synthesis options. Besides the advantage of greatly shortened design cycle, experimental results do show the competitiveness of the automatically generated designs against the manual designs.
URI: http://hdl.handle.net/11455/8523
其他識別: U0005-1708200919553200
Appears in Collections:電機工程學系所

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