Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8549
標題: 應用於液晶顯示器之緩衝放大電路設計
Design of Buffer Amplifier for LCD Applications
作者: 施秉昇
Shih, Ping-Sheng
關鍵字: 液晶顯示器;LCD;緩衝放大器;Buffer amplifier
出版社: 電機工程學系所
引用: [1] 汪芳興,“非晶矽薄膜電晶體液晶顯示器驅動電路積體電路技術”,電子月刊, 頁數:98-108, 2003 年8 月。 [2] 戴亞翔, TFT-LCD 面板的驅動與設計, 五南圖書出版, 民國95 年4月。 [3] Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design”, NewYork: Oxford, 2002. [4] Behzad Razavi, Design of Analog CMOS Integrated Circuit, New York:McGRAW- HILL, 2001. [5] 林振華, MOS類比電路, 全華科技圖書出版, 民國89 年1月。 [6] R.Hogervorst, R.J.Wiegerink, P.A.L de jong, J.Fonderie, R.F.Wassenaar and J.H.Huijsing “CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2876-2879, 1992. [7] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage,” IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 146-156, 1996. [8] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm inputstage architecture for low-voltage op amps,” IEEE Trans. Circuits and Systems-I, vol. 42. no. 11, pp. 886-895, 1995. [9] S. Sakurai and M. Ismail, Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation, Kluwer Academic Publishers, 1995. [10] S. A. Mahmoud and A. M. Soliman, "The differential difference operational floating amplifier: a new block for analog signal processing," IEEE Trans. Circuits Syst. II, pp.148-158, 1998. [11] 戴亞翔, ”TFT-LCD 面板的驅動與設計, 五南圖書出版, 民國95年4月。 [12] Tetsuro Itaku, Hironori Minamizaki, Tetsuya Satio, and Tadashi Kuroda, “A 402-Output TFT-LCD Driver IC With Power Control Based on the Number of Colors Selected,” IEEE Journal of Solid-State Circuits, Vol. 38, No.3, March, pp. 503-510, 2003. [13] P.-C. Yu and J.-C. Wu, “A class-B output buffer for flat-panel-display column driver”, IEEE J. Solid-State Circuits, vol. 34, pp. 116–119, Jan. 1999. [14] C.-W. Lu, ”High-Speed Driving Scheme and Compact High-Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Applications”, IEEE J. Solid-State Circuits, 2004, pp. 1938-1947. [15] SU Li, QIU Yulin, “Design of a Fully Differential Gain-Boosted Folded-Cascode Op Amp with Settling Performance Optimization”, IEEE 2005, pp. 441- 444. [16] Chih-Wen Lu , “A HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR LCD APPLICATION”, IEEE 2006, PP. 709 – 712. [17] Pang-Cheng Yu and Jiin-Chuan Wu, “A Class-B Output Buffer for Flat-Panel-Display Column Driver,” IEEE Journal of Solid-State Circuits, 1999, pp. 116-119. [18] Ming-Chan Weng and Jiin-Chuan Wu, “A Compact Low-Power Rail-to-Rail Class-B Buffer for LCD Column Driver,” IEICE Trans. Electron 2002, pp. 1659-1663. [19] Jinyong Choi, Kyungyoul Min and Changsik Yoo , “High-Speed and Low-Power Analog Source Driver for TFT-LCD Using Dynamic Current Biased Operational Amplifier”, SID 2007, pp. 1647- 1650. [20] David A. Johns, Ken Martin, “Analog integrated circuit design, John Wiley & Sons, 1997. [21] Falk Roewer, Ulrich Kleine , “A novel class of complementary folded-cascode opamps for low voltage”, IEEE JSSC 2002, pp.1080 -1083. [22] P. K. Chan, L. Siek, H.C. Tay, J.H. Su, A Low-Offset Class-AB CMOS Operational Amplifier, ISCAS 2000, pp. 455-458.
摘要: 
本論文提出可應用於液晶顯示器上的緩衝放大電路。論文探討傳統緩衝放大電路的缺點並且加以改善。設計製程是採用TSMC 0.35μm 2P4M CMOS 3.3V製程製作緩衝放大電路,並且將所設計的緩衝放大電路分兩章討論。

本論文提出的第一種緩衝放大電路,電路偏壓部分是採用穩定性佳且不受電源因素影響的疊接電流源作為偏壓電路,輸入以P型和N型差動對作為互補式輸入級,以疊接放大器作為增益放大級,輸出則使用Class B放大器作為輸出級,使得輸入與輸出範圍可由0 V ~ 3.3 V,具有軌對軌之特性,以五級2 KΩ || 30 pF的電阻電容網路模擬液晶顯示器面板上資料線之負載。

若要使液晶顯示器的色彩深度(color depth)能夠大幅提升,就必須採用位元數較高的數位類比轉換電路(DAC),也就表示其輸出的每一灰階類比電壓值的差將會隨著位元數的增加而變小,因此輸出緩衝放大器的偏移電壓(offset voltage)就顯的特別重要。本論文所提出的第二種輸出緩衝放大電路特別針對偏移電壓做更進一步的改善,利用疊接放大器與共源極放大器來提升緩衝放大器的電壓增益,減少偏移電壓值,輸出級採用源極電壓隨偶器串接電流鏡所構成的Class AB放大器,以降低輸出級的消耗功率。

Design the buffer amplifier circuits which can be used for liquid crystal display (LCD). Researches on the drawbacks of convention buffer amplifier circuit and improve the design. Designs two different buffer amplifier circuits on TSMC 0.35μm 2P4M CMOS 3.3V supply voltage process, and divides the buffer amplifier circuit into two chapters.
In this work, buffer amplifier circuit I. The bias circuit adopts stable folded -cascode current source which can''t be influenced upon power supply factor and adopts PMOS and NMOS complementary input differential pairs, using folded -cascode amplifier for open-loop gain stage and the output stage used class B amplifier. In this work, the first buffer of input and output range from 0 V to 3.3 V to achieve rail to rail with 2 KΩ resistive and 30 pF capacitive network loading of TFT-LCD panel.
In order to application on high resolution of liquid crystal display (LCD), which must reduce differential error voltage in digital-to-analog converter(DAC) circuit. So, how to reduce the offset voltage of buffer amplifier is important. In the second buffer amplifier circuit, to promote the open-loop gain to reduce offset voltage. We uses folded -cascode amplifier and common source to promote the open-loop gain in buffer II to reduce offset voltage. The output stage used Class AB amplifier, it consists of voltage source follower cascade current source, to reduce power consumption.
URI: http://hdl.handle.net/11455/8549
其他識別: U0005-1808200917503100
Appears in Collections:電機工程學系所

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