Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8551
標題: 適用於H.264/AVC以及VC-1視訊標準之重疊平滑濾波器與雙模式區塊消除濾波器電路架構設計與實作
Design and implementation of overlap smoothing and dual-mode deblocking filter for H.264/AVC and VC-1 applications
作者: 陳建廷
Chen, Chein-Ting
關鍵字: Overlap Smoothing;重疊平滑濾波器;Deblocking filter;H.264/AVC;VC-1;區塊消除濾波器
出版社: 電機工程學系所
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Schwarz, T. Wiegand, and G. J. Sullivan, “Performance comparison of video coding standards using Lagragian coder control,“ in Proceedings of IEEE International Conference on Image Processing (ICIP'02). 2002, pp. 501- 504. [9] T. Koga, K. Iinuma, A. Hirano, Y. Iijima and T. Ishiguro, “Motion compensated interframe coding for video conferencing,” in Proc. Nut. Telecommun. Conf., pp. G5.3.1-5.3.5, Nov. 1981. [10] J. Y. Tham, S. Ranganath, M. Ranganath, and A. A. Kassim, “A Novel Unrestricted Center-Biased Diamond Search Algorithm for Block Motion Estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 4, pp. 369- 378, Aug. 1998. [11] S. Zhu and K.-K. Ma, “A New Diamond Search Algorithm for Fast Block- matching Motion Estimation,” IEEE Transactions on Image Processing, vol. 9, pp. 287-290, Feb. 2000. [12] A.Puri, X.Chen, and A.Luthra, “Video coding using the H.264/MPEG-4 AVC compression standard,” IEEE Transactions on. Signal Processing: Image Commuication., pp. 793-849, 2004. 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Multimedia and Expo, Vol. 1, pp. I-693 - I-696, July 2003. [19] C.-C. Cheng, and T.-S. Chang, “An Hardware Efficient Deblocking Filter for H.264/AVC,” in Proc. Int. Conf. Consum. Electron., pp. 235-236, Jan. 2005. [20] S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A Platform Based Bus-interleaved Architecture for Deblocking Filter in H.264/MPEG-4 AVC,” IEEE Trans. Consum. Electron., vol. 51, no. 1, pp. 249-255, Feb. 2005. [21] C.-C Cheng, T.-S. Chang, and K.-B. Lee, “An in-place architecture for the deblocking filter in H.264/AVC,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 53, no. 7, July 2006. [22] T.-M. Liu, W.-P. Lee, T.-A. Lin, and C.-Y. Lee, “A Memory-Efficient Deblocking Filter for H.264/AVC Video Coding,” in Proc. Int. Symp. Circuits Syst., vol. 3, pp. 2140-2143, May 2005. [23] Y.-W. Huang, T.-W. Chen, B.-Y. Hsieh, T.-C. Wang, T.-H. Chang and L.-G. Chen, “Architecture Design for Deblocking Filter in H.264/JVT/AVC” in Proc. Int. Conf. Multimedia and Expo, Vol. 1, pp. I-693 - I-696, July 2003. [24] S.-Y. Shih, C.-R. Chang, and Y.-L. Lin, “An AMBA-Compliant Deblocking Filter for H.264/AVC,” in Proc. Int. Symp. Circuits Syst., vol. 1, pp. 4529 - 4532, May 2005 [25] C.-C. Cheng, and T.-S. Chang, “An Hardware Efficient Deblocking Filter for H.264/AVC,” in Proc. Int. Conf. Consum. Electron., pp. 235-236, Jan. 2005. [26] B. Sheng, W. Gao, and D. Wu, “An Implemented Architecture of Deblocking Filter for H.264/AVC,” in Proc. Int. Conf. Image Process., vol. 1, pp. 665-668, Oct. 2004. [27] T.-M. Liu, W.-P. Lee, T.-A. Lin, and C.-Y. Lee, “A Memory-Efficient Deblocking Filter for H.264/AVC Video Coding,” in Proc. Int. Symp. Circuits Syst., vol. 3, pp. 2140-2143, May 2005. [28] L. Li, S. Goto, and T. Ikenaga, “A Efficient Deblocking Filter Architecture with 2-dimensional Parallel Memory for H.264/AVC,” in Proc. IEEE Asia and South Pacific Design Automation Conf., vol. 1, pp. 623-626, Jan. 2005. [29] M. Sima, Y. Zhou, and W. Zhang, “An Efficient Architecture for Adaptive Deblocking Filter of H.264/AVC,” IEEE Trans. Consum. Electron., vol. 50, no. 1, pp. 292-296, Feb. 2004. [30] S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A Platform Based Bus-interleaved Architecture for Deblocking Filter in H.264/MPEG-4 AVC,” IEEE Trans. Consum. Electron., vol. 51, no. 1, pp. 249-255, Feb. 2005. [31] Y. Lin and T. Q. Nguyen, “Analysis and efficient architecture design for VC-1 overlap smoothing and in-loop declbocking filter,” IEEE Trans. Circuits Syst. Video Technol., vol. 18, no. 12, pp. 1786-1796, Dec. 2008. [32] Y.-K. Lai, L.-G. Chen, T.-H. Tsai, and P.-C. Wu, “A novel scalable architecture with memory interleaving organization for full search block-matching algorithm,” in Proc. Int. Symp. Circuits Syst., vol. 2, pp. 1229-1232, June 1997. [33] Y.-K. Lai, “A memory efficient motion estimator for three step search block-matching algorithm,” IEEE Trans. Consum. Electron., vol. 47, no. 3, August 2001. [34] K-Y. Min, J-W Chong “A memory and performance optimized architecture of deblocking filter in H.264/AVC,”IEEE Multimedia and Ubiquitous Engineering, 2007, (MUE'07) pp. 220-225, April 2007. [35] T-M. Liu, W-P Lee “An in/post-loop deblocking filter with hybrid filtering schedule,” IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 7, pp. 937-943, July. 2007. [36] Philip Dang “High performance architecture of an application specific processor for the H.264 deblocking filter,” IEEE Trans. VLSI Syst., vol. 16, no. 10, pp. 1321-1334, Oct. 2008. [37] Ke Xu, C-S Choy “A five-stage pipeline, 204 cycles/MB, single-port SRAM-Based deblocking filter for H.264/AVC,” IEEE Trans. Circuits Syst. Video Technol., vol. 18, no. 3, pp. 363-374, March. 2008. [38] C-A Chien, H-C Chang, and J-I Guo “A high throughput deblocking filter design supporting multiple video coding standards,” Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium., pp. 2377-2380, May 2009.
摘要: 
在本篇論文中,我們提出了一個工作於62.5 MHz可達到每秒鐘30張畫面的Full HD 1080P畫面大小之重疊平滑濾波器與雙模式區塊消除濾波器架構。這個架構可以支援H.264/AVC和VC-1兩種視訊標準之區塊消除濾波器,此外,在VC-1視訊標準中我們還將重疊平滑濾波器整合到我們的區塊消除濾波器。透過很多文獻和實作的結果我們可以知道,記憶體對於區塊消除濾波器的速度和硬體成本有很大的影響,因此我們提出記憶體插補技術,利用有效率的記憶體存取方式,不但能有效的減少內建記憶體使用量和記憶體頻寬,還能夠有效的提升運算速度,並透過區塊管線以及有效的資料排程等方式提升運算速度。我們還提出了改良式二維處理程序之混合型資料排程來有效安排運算的流程,在不改變原本相鄰區塊特性的前提下,將原本的資料排程改善為有效率的資料排程,使得我們的資料重複使用等級能達到Level B,也就是對於垂直與水平邊界相鄰區塊皆能夠做到資料重複使用。使用我們所提出的記憶體插補技術配合我們所提出的改良式二維處理程序之混合型資料排程能夠很有效的提升運算速度減少內建記憶體使用量降低外部記憶體頻寬。
最後我們採用TSMC Artisan 0.18µm cell library的製程將電路進行實作,結果顯示本架構可於62.5 MHz的頻率下順利完成Full HD 1080P@30fps的區塊消除濾波器的運算,根據實作結果晶片的面積為880X880 um2。本電路可以應用於多種編碼器和解碼器之中。另外,由於本電路可以適用於兩種不同之視訊標準中,因此可以更多樣化的支援多種不同的編碼器與解碼器。

In this thesis, a VLSI architecture of the overlap transform and duel-mode deblocking filter is proposed for HD1080p applications. This deblocking filter architecture can support both H.264/AVC and VC-1 video standards. In addition, the overlap smoothing transform also combines with the deblocking filter while VC-1 standard is performed. Many literatures and the results of the chip implementation show that the memory organization dominates the hardware cost and the throughput rate of the deblocking filter. In order to increase throughput and to reduce on-chip memory and memory bandwidth, we propose the memory interleaving techniques to arrange data in the on-chip memory and to efficiently access the data in both horizontal and vertical filters. We also utilize the hybrid schedule for the two-dimensional (2-D) processing order to reduce the total on-chip memory size. According to our proposed memory interleaving organization, the memory interlacing configuration and the hybrid schedule of the 2-D processing order can speed up the throughput and reduce the memory bandwidth efficiently.
Finally, we implement our architecture by using TSMC Artisan 0.18µm cell library, and the clock frequency of the proposed architecture is 62.5-MHz. The implementation result shows that the core size is 880X880 um2. Because of the duel-mode character, our architecture can be applied to multiple encoders and decoders.
URI: http://hdl.handle.net/11455/8551
其他識別: U0005-1808200918351300
Appears in Collections:電機工程學系所

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