Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8554
標題: 以機率模型為基礎之具有提早中止機制整數移動估測電路架構
Fast integer motion estimation architecture based on model-based early termination scheme
作者: 廖啟耀
Liao, Chi-Yao
關鍵字: integer motion estimation;整數點移動估算;variable block size;HD720p;H.264/AVC;可變區塊大小;HD720p;H.264/AVC
出版社: 電機工程學系所
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摘要: 
移動估算是視訊編碼系統的最重要的部分,在編碼器中,需要最多運算量與記憶體存取。其中,又以H.264/AVC為目前最新的國際視訊編碼標準,相較於MPEG-4、H.263、和MPEG-2,它可分別節省37%、48%、和64%的資料量。

本論文首先將會介紹最近二十年來(1981-2006)其中最重要的移動估算演算法和架構。然後我們提出一個基於二階段漸進的快速演算法,並將其套用於H.264/AVC中整數點移動估算架構上,此快速演算法可保有和全搜尋相當的視訊品質,並只需要多重區塊大小之全區域搜尋區塊比對演算法5%的運算量。再來我們提出一個基於機率模型的提早中斷移動估算演算法,利用演算法中所求得的方程式計算出各種電力模式與量化係數下的門檻值,並與原點及移動向量預測點所得之SAD值比較,如果小於門檻值就停止移動估算器動作,達到節省運算量的效果。接下來,為了降低高精準度移動估算所需的運算時間,加入一個以SATD為基礎的預先模式選擇演算法,此快速演算法符合JM來源碼的模式選擇方式。最後整合我們提出的快速整數點移動估算與高精準度移動估算,完成H.264/AVC幀間畫面預測引擎的設計與實現。

二階段漸進的快速移動估算器,實作上採用標準單元以及TSMC 0.18um 1P6M製程實作,最高工作頻率為62.5 MHz,可處理HD720p(1280 × 720)的畫面,消耗功率為194.0 mW,晶片面積為3.20 × 3.58 mm2。加入提早中斷移動估算與預先模式選擇演算法後,採用標準單元以及UMC Faraday 90nm 1P9M製程實作,晶片實作結果,最高工作頻率為62.5 MHz,可處理HD720p(1280 × 720)的畫面,量化參數為32時,功率消耗為15.75mW到40.70 mW,最高可省略61%的功率消耗,晶片面積為2.38× 2.37 mm2。

簡而言之,我們提出的架構,為目前最高效能的H.264/AVC整數點移動估算架構,支援HD720p的畫面,且具有低功率消耗以及低硬體面積。我們由衷的希望我們提出的概念,能對數位影像帶來進步。

Motion estimation is the most important part, and requires the most computing power and memory access in the video encoder. Compared with previoius standards such as MPEG-4, H.263, and MPEG-2, H.264/AVC is the latest international video coding standard, and can save 37%, 48%, and 64% bit-rates respectively. In the first part of this thesis, we introduce main motion estimation algorithms and architectures during the last two decades (1981-2006).

Second, we propose a fast motion estimation algorithm based on the coarse-to-fine technique. The proposed algorithm is applied to integer motion estimator of the H.264 encoder, and performs the local full search on pixels around the selected candidates to obtain the 41 MVs. Our algorithm can preserve the same quality as FS, but the complexity of it is about 5% of the variable block size (VBS) full search. Moreover, we propose an early motion termination algorithm based on the model-based scheme. The threshold values are determined by the quantization parameter (QP) and power budget. To reduce operation, we compare SAD values with threshold values. If the SAD value is smaller than the threshold value, motion estimation will be terminated. In addition, we introduce the SATD-based pre-mode decision algorithm to reduce caculation lantency of fractional motion estimation. The proposed algorithm is the same as the mode decision of the reference source code. Overall, we integrate fast integer motion estimation and fractional motion estimation to implement the H.264/AVC inter prediction engine.

Our motion esitimation with two-step coarse-to-fine technique has been implemented by using standard cell methodology for TSMC 0.18um 1P6M technology. The proposed architecture can process HD720p resolution pictures in 30 frames per second at 59.6 MHz. Also, it can work at 62.5 MHz and the power consumption is about 194 mW. The chip size is 3.20 3.58 mm2. Besides, the integer motion estimation with our three fast algorithms has been implemented by using standard cell methodology for UMC Faraday 90nm 1P9M technology. When QP is 32,the power consumption is about 15.75~40.70 mW. The chip size is 2.38 2.37 mm2.

In conclusion, our integer motion estimation architectures and can support HD720p video format in H.264/AVC application. This architecture has low power consumption and low hardware cost.
URI: http://hdl.handle.net/11455/8554
其他識別: U0005-1808200918463100
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