Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8562
標題: 適用於H.264/AVC視訊之高精確度移動估計引擎快速演算法分析以及架構設計與實現
Fast Algorithm Analysis and Architecture Design of the Fractional Motion Estimation for H.264/AVC Applications
作者: 方冠傑
Fang, Guan-Jie
關鍵字: 移動估測;Early termination;幀間模式決策;H.264/AVC;H.264/AVC;inter mode decision;motion estimation;skip mode;VLSI
出版社: 電機工程學系所
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摘要: 
幀間預測因為著多重區塊大小的幀間模式決策,造成為H.264/AVC運算量及功耗最主要的部份。於是為了設計低功率和電力調整的系統,我們提出了兩個硬體適性的快速演算法來大幅度降低整體功率的消耗。而這兩種演算法與整數點移動估測快速演算法(Interger motion estimation)[57]整合來完成我們提出的幀間預測架構,可達到HDTV720p的應用。
我們提出的第一個演算法,預先模式決策演算法(Inter Pre-Mode Decision),IME引擎利用每個模式切割最佳的SAD決定動作向量(Motion Vector),再把每個模式最佳的動作向量比較找出每個MB最佳SATD的幀間模式切割,進入浮點數移動估測(Fractional Motion Estimation),這樣可在IME級提早決定MB的最佳切割模式,並且可大幅減低FME的運算週期。
而第二個為以機率模型為基礎之具有提早中止機制整數移動估測演算法,我們基於移動估測的誤差(residue)轉換後的係數所統計的機率模型來提早中斷H.264/AVC幀間預測。根據幾個理論模型,我們統計並建立混合機率模型,而可更準確地計算出的多種情況的中斷門檻值,可以完成一個可電力調整機制的系統來提早中斷移動估測的運算。
模擬結果顯示提早中斷移動估測在不同的模式下可省去不同比例的MB估測。然而,我們定義的高畫質模式的R/D 曲線表現會跟原始JM模擬模型非常的貼近。實作上採用標準單元以及UMC 0.09um 1P9M製程實作,晶片實作結果顯示我們所提出的架構可以在工作頻率60MHz下完成HDTV720p即時編碼。最後,我們所提出的功率可調之快速幀間預測架構,在HDTV720p的應用時,四種模式功率消耗約33~55mW左右。

Inter prediction is the most power-consuming component in the H.264/AVC encoder because of the inter mode decision of the variable block-size motion estimation (VBSME) algorithm. For the low power and power-aware system design, the co-design methodology of the fast algorithm and hardware architecture is proposed to reduce the power consumption efficiently.
In the thesis, we propose two algorithms. First, the inter mode pre-decision, which is realized on the IME engine to early decide the macroblock (MB) partition, to substantially decrease the computational cycle counts of the fractional motion estimation (FME) engine, and to carry off the motion vector predictor (MVP). Moreover, the model-based early termination scheme, which is to early terminate the H.264/AVC inter prediction based on the statistical model of the transform coefficients. According to the theoretical model, we develop a power-aware adaptive mechanism with multiple thresholds derived from the statistical model to early terminate the ME operation.
The simulation results show that the early motion termination MB can save at different modes. Besides, based on our proposed high quality mode, the R-D performance curve is approximated by Reference source code(JM). The result of the chip implementation shows that our proposed architecture can achieve the real-time HDTV720p resolution at 60 MHz clock frequency with UMC 0.09um 1P9M process. Consequently, the power consumption of our proposed power-aware inter prediction architecture is about 33 ~ 55 mW for the HDTV720p applications in four different power modes.
URI: http://hdl.handle.net/11455/8562
其他識別: U0005-1808200919101800
Appears in Collections:電機工程學系所

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