Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8591
標題: N通道低溫複晶矽薄膜電晶體操作在交流訊號下關閉區域之可靠性研究
Study on the Reliability of N-Channel Low Temperature Poly-Si Thin Film Transistors Dynamically Operated in OFF Region
作者: 王誌源
Wang, Jhih-Yuan
關鍵字: Reliability;複晶矽;LTPS;TFT;Off region;交流;關閉區域;可靠
出版社: 電機工程學系所
引用: 〔1〕 H. Kuriyama et al., “An asymmetric memory cell using a C-TFT for ULSI SRAM, ”Symp. On VLSI Tech., 1992. 〔2〕 Yamauchi, N.; Inaba, Y.; Okamura, M, “An integrated Photodetector-amplifier using a-Si p-i-n photodiodes and poly-Sithin-film transistors, ”IEEE Photonics Technology Letters, Volume 5, Issue 3, 1993. 〔3〕 T. Yamanaka, T.Hashimoto, N.Hasegawa, T. Tanala, N. Hashimoto, A Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E.Takeda, and T.Nagano, “Advanced TFT SRAM cell technology using a phase-shift lithography, ” IEEE transaction on electron device, Volume. 42, 1995. 〔4〕 Young, N.D.; Harkin, G.; BUNN, R.M.; McCulloch, D.J.; Wilks, R.W.; Knapp, A.G, “Novel fingerprint scanning arrays using polysilicon TFTs on glass And polymer substrates, ”IEEE, Electron Device Letters, Volume 18,Issue 1, 1997. 〔5〕 Young, N.D.; Harkin, G.; Bunn, R.M.; McCulloch, D.J.; French, I.D., “The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process, ”IEEE transaction on electron device, Volume43, Issue 11, 1999 〔6〕 Kow Ming CHANG, Yuan Hung CHUNG and Gin Ming LIN, “Hot Carrier Induced Degradation in Low Temperature Processed Polycrystalline Silicon Thin Film Transistors Using the Dynamic Stress, ”Japanese Journal of Applied Physics Volume.41, No.4A, 2002. 〔7〕 Yukiharu URAOKA, Koji KITAJIMA, Hiroshi KIRIMURA, Hiroshi YANO, Tomoaki HATAYAMA and Takashi FUYUKI, “Degradation in Low-Temperature Poly-Si Thin Film Transistors Depending on Grain Boundaries, ”Japanese Journal of Applied Physics Volume.44, No.5A, 2005. 〔8〕 Satoshi INOUE, Mutsumi KIMURA and Tatsuya SHIMODA“Analysis, “Classification of Degradation Phenomena in Polycrystalline-Silicon Thin Film Transistors Fabricated by a Low-Temperature Process Using Emission Light Microscopy, ”Japanese Journal of Applied Physics. Volume.42, 2003 〔9〕 Kook Chul Moon, Jas-Hoon Lee, and Min-Koo Han,“The Study of Hot-Carrier Stress on Poly-Si TFT Employing C-V measurement, ”IEEE transaction on electron device, Volume.52, NO.4, 2005 〔10〕 Yukiharu Uraoka, Hiroshi YANO, Tomoaki HATAYAMA and Takashi FUYUKI, “Comprehensive Study on Reliability of Low-Temperature Poly-Si Thin-Film Transistors under Dynamic Complimentary Metal-Oxide Semiconductor Operations, ”Japanese Journal of Applied Physics. Volume.41, 2002 〔11〕 Ya-Hsiang Tai, Shih-Che Huang, and Po-Ting Chen, “Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region, ” IEEE ELECTRON DEVICE LETTERS, Volume. 30, No.3, 2009 〔12〕 Yukiharu URAOKA∗, Hiroshi YANO, Tomoaki HATAYAMA and Takashi FUYUKI, “Hot Carrier Effect in Low-Temperature poly-Si p-ch Thin Film Transistors under Dynamic Stress, ” Japanese Journal of Applied Physics. Volume.41, 2002 〔13〕 Yukiharu Uraoka, Noboyuki Hirai, Hiroshi Yano, Tomoaki Hatayama, and Takashi Fuyuki, “Hot Carrier Analysis in Low-Temperature Poly-Si TFTs Using Picosecond Emission Microscope, ” IEEE transaction on electron device, Volume.51, NO.1, 2004 〔14〕 Ya-Hsiang Tai, Shih-Che Huang, and Chien-Kwen Chen, “Analysis of Poly-Si TFT Degradation Under Gate Pulse Stress Using the Slicing Model, ” IEEE transaction on electron device, Volume.27, NO.12, 2006 〔15〕 Yukiharu Uraoka, Tomoaki Hatayama, Takashi Fuyuki, Tetsuya Kawamura, and Yuji Tsuchihashi, “Reliability of Low Temperature Poly-Silicon TFTs Under Inverter Operation, ” IEEE transaction on electron device, Volume.48, NO.10, 2001 〔16〕 Chin-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Sieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, and Tan-Fu Lei, “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors,”IEEE transactions on electron devices, Volume.53, No.12, 2006.
摘要: 
低溫複晶矽薄膜電晶體目前被廣泛的應用,因此研究低溫複晶矽薄膜電晶體可靠度是一件很重要的議題。當低溫複晶矽薄膜電晶體應用於液晶面板顯示器上時,是利用交流訊號於閘極端來控制元件開關,資料訊號於汲極端。而當元件正常運作時,必定會觸及導通區域及關閉區域。從我們的實驗結果中,可以發現,當元件操作在關閉區域時,比操作於導通區域時有更大的元件特性衰退量。故本篇論文中,我們將探討低溫複晶矽薄膜電晶體操作在關閉區域時之可靠度研究。

在第一部份中,我們於閘極端給予交流訊號作電壓應力測試,分析元件電性特性隨應力時間變異之關係。從實驗中,我們發現元件操作關閉區域時,有非常顯著的衰退量。並且隨著頻率增加,衰退量也會明顯的上升。我們提出一個衰退模型來解釋元件的衰退機制。並且嘗試著不改變元件架構下,利用取樣電流、電容-電壓量測、順向反向電流-電壓量測來驗證我們所提出的衰退模型。

在第二部分中,我們除了於閘極端給予交流訊號,並且於汲極端給予直流訊號作電壓應力測試。使電壓應力測試更接近真實的元件操作情形。從實驗中,我們發現元件操作在關閉區域下,在較低頻時,汲極端給予-5V直流電壓其衰退量會比汲極端給予+5V直流電壓之衰退量來的大。而在較高頻時,結果剛好相反。我們利用取樣電流、電容-電壓量測、順向反向-電流電壓量測來證實我們所提出的主要傷害區域及衰退機制模型。

LTPS (Low Temperature Poly-Si) TFTs have been widely used recently. Therefore, the study of LTPS reliability is one of the most important issues. When the LPTS TFTs were worked on the liquid crystal display, the TFT's On/Off states are controlled by AC signal on the gate, data signal on the drain. When the TFTs normally work, they would be toggled in the OFF region. From the results of experiment, we could find that the TFTs operated in the Off region had larger degradation than it operated in the On region. Thus, in this thesis, we will study the reliability of the LTPS TFTs operated in Off region.

In the first part, the gate of TFTs under AC signal stress were had to analysis the relationship between the characteristic of TFTs and stress time. In our experiments, we could find that there were obvious degradation, when TFTs were operated in the Off region. Moreover, the degradation of TFTs increased as well as the frequency increasing. We proposed a degradation model to explain the degradation mechanisms of TFTs. We used three measuring items, sampling current measurement, C-V measurement and Forward Reverse-IV measurement, to verify the degradation model we presented.

In the second part, we apply AC signal stress on the gate and DC signal stress on the drain. Let the bias stress approach the real operation of TFTs. In our experiments, we could find that TFTs stressed in the low frequency, Vd=-5V condition had larger degradation than Vd=+5V condition. The TFTs stressed in the high frequency, Vd=+5V condition had larger degradation than Vd=-5V condition. We also used three measuring items, sampling current measurement, C-V measurement and Forward Reverse-IV measurement, to verify the degradation model we presented.
URI: http://hdl.handle.net/11455/8591
其他識別: U0005-2007200914501400
Appears in Collections:電機工程學系所

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